Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

Semiconductor integrated circuits with power reduction mechanism

A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more.

Semiconductor Integrated circuit

A command buffer for use in packetized DRAM includes a four stage shift register for shifting for sequentially storing four 10-bit command words. The shift register combines the four 10-bit command words into a single 40-bit command word and transfer the 40-bit command word to a storage register for processing by the DRAM. The shift register may then continue to receive and store subsequent 10-bit command words. The command buffer also includes circuitry for determining whether a command packet is intended for the memory device containing the command buffer or whether it is intended for another memory device. Specifically, a portion of the 40-bit command word from the storage register is compared to identifying data stored in an identifying latch. In the event of a match, a chip select signal is generated to cause the memory device to perform the function corresponding to other portions of the 40-bit command word. The identifying latch is programmed with the unique identifying data during power-up by storing the identifying data responsive to an initialization command packet. The shift register includes shift register circuits that are specifically adapted to operate at very high speeds.

Two step memory device command buffer apparatus and method and memory devices and computer systems using same

A multiple compound CMOS domino circuit (234) is disclosed having a first input section (248) connected to a preliminary dynamic output node (244). A second input section (250) is connected to a preliminary output dynamic node (246) which is independent of the first dynamic node (244). Separate precharge devices (236, 238) precharge the respective dynamic nodes (244, 246) to a desired voltage. Separate discharge transistors (240, 242) operate in conjunction with the respective input sections (248, 250) to discharge the dynamic nodes (244, 246). Static output logic gates (252, 254) include inputs connected to the dynamic nodes (244, 246) and provide multiple outputs of the compound domino logic circuit (234).

Multiple compound domino logic circuit

A method and apparatus for processing pipelined command packets in a packetized memory device. The command packets are initially stored in one of several command units, and the commands are subsequently coupled to a common command processor for execution. The command units each include a latch for storing a command packet, a counter, and a start command generator. The counter is preloaded with a count corresponding to the timing that the command is received at a location within the memory device. The counter begins counting responsive to a flag bit received with the command packet. The start command generator receives the count of the counter, and decodes different counts depending on the type of command (e.g., a “read” or a “write”) and the speed of a clock signal that is used to control the operation of the memory device. When the start command generator decodes a count, it latches command bits of the applied command packet and generates a start command signal. Thus, the start command signal is generated after the flag signal by a delay that corresponds to the type of memory command and the clock speed. The latched command bits and the start command signal are applied to a command processor that executes the commands in a pipeline using a sequencer to generate a sequence of timing signals, and a state machine to generate command signals from the latched command bits.

Method and system for processing pipelined memory commands

Described herein is a dynamic latch circuit having a pair of control terminals connected to receive complementary first and second control clock pulses which are generated at a predetermined frequency, and a register section for detecting the voltage of an input signal, in response to each of the first and second control clock pulses, and generating an output signal from a capacitive output node which is charged or discharged in accordance with the voltage of the input signal and is subsequently set at a low potential or a high potential. The latch circuit further comprises a voltage-generating circuit for detecting, based on a period of time elapsed from the trailing edge of the last generated first control clock pulse, that the supply of the first control clock pulses has been stopped and fixedly setting the output node at the low potential.

Dynamic latch circuit for preventing short-circuit current from flowing during absence of clock pulses when under test

PURPOSE:To prevent a through-current from flowing when a control clock is fixed by detecting the stop state where the control clock reaches a DC level and controlling the conduction of a switching element throughout this stop period. CONSTITUTION:The switching element T10 is interposed between the output terminal of a clocked inverter circuit C2 which is driven and controlled with the control clock and one high or low power source potential supply terminal, and the stop state wherein the control clock reaches the DC level is detected to control the conduction of the switching element T10 by a control means 11 throughout the stop period. Namely, the switching element is turned on to hold the output terminal of the clocked inverter circuit at a high or low potential, so even if the control clock is broken, the output of the clocked inverter circuit C2 never varies to an intermediate potential. Consequently, a through-current is prevented from flowing between power source terminals.

Miyashita Toshiyuki

Papers

Dynamic latch circuit for preventing short-circuit current from flowing during absence of clock pulses when under test

Semiconductor integrated circuit