Secure Multi-party Computation (MPC) allows a set of mutually distrusting parties to jointly evaluate a function on their private inputs while maintaining input privacy. In this work, we improve semi-honest secure two-party computation (2PC) over rings, with a focus on the efficiency of the online phase. We propose an efficient mixed-protocol framework, outperforming the state-of-the-art 2PC framework of ABY. Moreover, we extend our techniques to multiinput multiplication gates without inflating the online communication, i.e., it remains independent of the fan-in. Along the way, we construct efficient protocols for several primitives such as scalar product, matrix multiplication, comparison, maxpool, and equality testing. The online communication of our scalar product is two ring elements irrespective of the vector dimension, which is a feature achieved for the first time in the 2PC literature. The practicality of our new set of protocols is showcased with four applications: i) AES S-box, ii) Circuit-based Private Set Intersection, iii) Biometric Matching, and iv) Privacypreserving Machine Learning (PPML). Most notably, for PPML, we implement and benchmark training and inference of Logistic Regression and Neural Networks over LAN and WAN networks. For training, we improve online runtime (both for LAN and WAN) over SecureML (Mohassel et al., IEEE S&P’17) in the range 1.5×–6.1×, while for inference, the improvements are in the range of 2.5×–754.3×.

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ABY2.0: Improved Mixed-Protocol Secure Two-Party Computation.

Improving the accuracy of a neural network (NN) usually requires using larger hardware that consumes more energy. However, the error tolerance of NNs and their applications allow approximate computing techniques to be applied to reduce implementation costs. Given that multiplication is the most resource-intensive and power-hungry operation in NNs, more economical approximate multipliers (AMs) can significantly reduce hardware costs. In this article, we show that using AMs can also improve the NN accuracy by introducing noise. We consider two categories of AMs: 1) deliberately designed and 2) Cartesian genetic programing (CGP)-based AMs. The exact multipliers in two representative NNs, a multilayer perceptron (MLP) and a convolutional NN (CNN), are replaced with approximate designs to evaluate their effect on the classification accuracy of the Mixed National Institute of Standards and Technology (MNIST) and Street View House Numbers (SVHN) data sets, respectively. Interestingly, up to 0.63% improvement in the classification accuracy is achieved with reductions of 71.45% and 61.55% in the energy consumption and area, respectively. Finally, the features in an AM are identified that tend to make one design outperform others with respect to NN accuracy. Those features are then used to train a predictor that indicates how well an AM is likely to work in an NN.

Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers

Fuzzy systems, neural networks and neuro-fuzzy systems: A vision on their hardware implementation and platforms over two decades

Biped walking by using all joint movements and DOFs in both directions (sagittal plane and coronal plane) is one of the most complicated research topics in robotics In this paper, angular trajectories of a stable biped walking for a humanoid robot are generated by a Truncated Fourier Series (TFS) approach The movements of legs and arms in sagittal plane are implemented by an optimized gait generator and a new model is proposed that can also produce the movement of legs in coronal plane based on TFS Particle Swarm Optimization (PSO) is used to find the best angular trajectories and optimize TFS Experimental results show that the using joints movements in sagittal and coronal planes to compose the walking skill allowed the biped robot to walk faster than previous methods that only used the joints in sagittal plane

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Biped walking using coronal and sagittal movements based on truncated fourier series

This paper presents a mixed-signal hybrid CMOS/Nano circuit to implement a fully programmable fuzzy processor that performs the zero-order Sugeno's algorithm. The programmability is incorporated in both the rule base and the membership function generator. Membership functions are stored in a memristor-based crossbar array, whereas digital memory is utilized to form a rule base. Each linguistic value whose shape can be independently chosen is stored in each row of the crossbar. Moreover, the adjacent linguistic values can have any order of overlapping ratio. Consequently, a very powerful and flexible fuzzifier is designed. The analog signal processing blocks are designed in both current and voltage mode to simplify the circuit complexity while the digital circuitry is utilized to add programmability to the whole processor. A fuzzy logic controller with nine rules, two inputs, and one output was successfully simulated using HSPICE with 350 nm technology. Simulation results confirm the proper operation of the processor that can operate up to 10 MFLIPS (Mega Fuzzy Logic Inference Per Seconds) while consuming 3.49 mW (@vdd 3.3v). Furthermore, simulation results show that an equivalent precision of 6-bits is achieved in the output signal generation. The circuit is laid out and it takes an area of approximately 0.614 mm2.

Design of a memristor based fuzzy processor

Humanoid research has made notable progress during the past 25 years. However, currently most humanoids use the ZMP (Zero Moment Point) for control of bipedal locomotion, which requires precise modeling and actuation with high control gains. On the contrary, researchers do not rely on such precise modeling and actuation. In this paper we have tried to introduce a novel method for the evolution of walking behavior in a simulated humanoid robot with up to 22 degrees of freedom. In this method a modified Truncated Fourier Series (TFS) generates walking angular trajectories and it is optimized by genetic algorithm. By studying human walking TFS parameters have also been reduced. As a test-bed, we chose Robocup 3D soccer simulation environment (spark) and implemented our method in MRL 3D team's agents. Experimental results show that training of the robot can be successfully performed by our method, thus allowing the biped robot to walk fast, stably and straightly.

A Truncated Fourier Series with genetic algorithm for the control of biped locomotion

Due to considerable effectiveness of the imprecise computing paradigm in hardware implementation of many applications, great attention has been recently paid by many research groups to develop different novel imprecise computational blocks such as adders and multipliers. Traditionally, the imprecise blocks are developed in an application independent manner, just similar to development of a conventional precise block. This article investigates the systematic application oriented development of the imprecise computational blocks which results in more customized components. The main focus is on the development of customized imprecise adder/multiplier for efficient implementation of a general multiply-accumulate (MAC) block as the basic building block of many imprecision tolerant applications including digital signal processing and soft computing. To develop some customized blocks for the MAC, the error behaviors of the suitable imprecise adder and multiplier are first extracted by analyzing the MAC. Based on analysis results, efficient small constant mean-error imprecise adder and multiplier are developed based on a systematic mathematical-logical approach. A wide range of synthesis and simulation results are provided to demonstrate efficiency of custom developed imprecise blocks with respect to some of the best existing imprecise blocks in a general MAC and a real 2D-Convolution application.

Small Constant Mean-Error Imprecise Adder/Multiplier for Efficient VLSI Implementation of MAC-Based Applications

An efficient fuzzification algorithm named as Dynamic Precision Fuzzification (DPF) is introduced in this paper which is mainly developed for hardware implementation. The DPF which might be generally used with any piecewise linear membership function, exploits an inherent capacity of the normal fuzzification algorithm to improve its efficiency when realized in a finite-precision implementation bed such as digital VLSI. The accuracy simulation results of the DPF and normal fuzzification method are presented and compared to show the superiority of the DPF. As the word-length is the most important parameter in a finite-precision implementation environment which determines the system cost-precision trade-off, the simulation results show that DPF provides suitable precision improvements with respect to traditional fuzzification without increasing the system word-length. The VLSI synthesis results of both methods are also presented to show that this considerable accuracy improvement is achieved by an acceptable increase in its VLSI implementation costs in terms of area, delay, and power consumption with respect to traditional methods.

A hardware oriented fuzzification algorithm and its VLSI implementation

Efficient utilization of imprecise computational blocks for hardware implementation of imprecision tolerant applications

Real-time image processing is used in a wide range of vision applications in recent years. Whereas these processing require very high speed and computational power, hardware implementation is a good choice for achieving high performance. In this paper a new low capacity and parallel architecture based on a special memory management and arithmetic unit is proposed for real-time spatial image processing. The architecture is implemented on FPGA at a 50 MHz clock frequency and a processing time of 5 ms for 3 times 3 generic window-based operations on 512 times 512 gray-scale images. Experimental results show that the proposed architecture outperforms the existing architectures in the area utilization aspect.

Mohammad Haji Seyed Javadi

Papers

A Truncated Fourier Series with genetic algorithm for the control of biped locomotion

Small Constant Mean-Error Imprecise Adder/Multiplier for Efficient VLSI Implementation of MAC-Based Applications

A hardware oriented fuzzification algorithm and its VLSI implementation

Efficient utilization of imprecise computational blocks for hardware implementation of imprecision tolerant applications

An Area-Efficient Hardware Implementation for Real-Time Window-Based Image Filtering