The fully integrated complementary metal-oxide-semiconductor (CMOS) transmitter (Tx), an essential component in every wireless communication system, ensures highly efficient signal processing and data transmission. The performance of the Tx significantly affects the overall performance of the wireless device [1]. The demand for low-power, low-cost wireless devices operating at the 2.4-GHz band has led to extensive research on RF architecture and circuit design. A well-defined architecture, including linear and simple functional block synthesis, is crucial to the design of the RF Tx for various applications [2]. The state-of-the-art CMOS Txs proposed in the literature to improve Tx performance analyses are vital to understanding application-oriented RF Tx design techniques for further research.

CMOS Transmitters for 2.4-GHz RF Devices: Design Architectures of the 2.4-GHz CMOS Transmitter for RF Devices

Power amplifiers (PAs) are among the most crucial functional blocks in the radio frequency (RF) frontend for reliable wireless communication. PAs amplify and boost the input signal to the required output power. The signal is amplified to make it sufficiently high for the transmitter to propagate the required distance to the receiver. Attempted advancements of PA have focused on attaining high-performance RF signals for transmitters. Such PAs are expected to require low power consumption while producing a relatively high output power with a high efficiency. However, current PA designs in nanometer and micrometer complementary metal–oxide semiconductor (CMOS) technology present inevitable drawbacks, such as oxide breakdown and hot electron effect. A well-defined architecture, including a linear and simple functional block synthesis, is critical in designing CMOS PA for various applications. This article describes the different state-of-the art design architectures of CMOS PA, including their circuit operations, and analyzes the performance of PAs for 2.4 GHz ISM (industrial, scientific, and medical) band applications.

https://www.mdpi.com/2079-9292/8/5/477/pdf

Design Architectures of the CMOS Power Amplifier for 2.4 GHz ISM Band Applications: An Overview

Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today’s devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as academia have put forward their innovations such as event-driven explicit time-coding, exponential-ratio array, switched RC bandgap reference circuit, etc., to make a trade-off between several performance parameters such as die area, ripple rejection, supply voltage range, and current efficiency. However, current LDO architectures in micro and nanometer complementary metal–oxide–semiconductor (CMOS) technology face some challenges, such as short channel effects, gate leakage, fabrication difficulty, and sensitivity to process variations at nanoscale. This review presents the LDO architectures, optimization techniques, and performance comparisons in different LDO design domains such as digital, analog, and hybrid. In this review, various state-of-the-art circuit topologies, deployed for the betterment of LDO performance and focusing on the specific parameter up-gradation to the overall improvement of the functionality, are framed, which will serve as a comparative study and reference for researchers.

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CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

This work presents a simulation study of the influence of temperature on the performance of dual material gate (DMG) vertical super-thin body (VSTB) FET. The introduction of DMG causes a drop in the off-state current (Ioff) by ~99.18% and DIBL by 20%. Drop in the Ioff enhances the on-to-off current ratio (Ion/Ioff) by ~98.85%. A rigorous investigation on temperature dependency of DC, analog/RF, and linearity metrics was carried out. The zero temperature coefficient (ZTC) bias point for the DMG device was observed to be nearly at a gate bias of VG = 0.41 V. Various DC figures of merit (FoM) such as subthreshold swing (SS), Ion/Ioff, and threshold voltage (VT) show improvement with temperature fall. Lowering in temperature also leads to enhanced analog/RF performance by offering superior gm, gd, Cgg, Cgd, maximum fT, maximum GBP, intrinsic delay, TGF, TFP, GFP, and GTFP. However, linearity metrics like gm2, gm3, VIP2, VIP3, IIP3, IMD3, and 1-dB compression point show better performance with an increase in temperature.

Study of Temperature Effect on Analog/RF and Linearity Performance of Dual Material Gate (DMG) Vertical Super-Thin Body (VSTB) FET

Level Shifter (LS) circuits are widely used as interfaces for multiple voltage domains in moderns ICs and System on Chips (SoCs). Low power dissipation and low delay are the main design considerations for high performance level shifters. This paper presents the design of a level shifter integrating new topological modifications to assure a wide range of voltage conversion with low power dissipation and low output delay. The presented level shifter is designed to take input signal of 1 V and convert that into an output signal of 1.8 V which is simulated in Silterra 0.13 μm CMOS process. The post layout simulation results show that the designed LS circuit has a significant low power dissipation of only 0.1449 nW and low output delay of 25.55 ps covering only 17.36× 14.560 μm2 chip area. Through detailed comparison with recently reported LS circuits, it has been shown that the proposed level shifter achieved a better performance in terms of power consumption, delay and compact chip size.

/pdf/design-of-a-low-power-cmos-level-shifter-for-low-delay-socs-4b6c45ja7i.pdf

Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process

The shift register is a type of sequential logic circuit which is mostly used for storing digital data or the transferring of data in the form of binary numbers in radio frequency identification (RFID) applications to improve the security of the system. A power-efficient shift register utilizing a new flip-flop with an implicit pulse-triggered structure is presented in this article. The proposed flip-flop has features of high performance and low power. It is composed of a sampling circuit implemented by five transistors, a C-element for rise and fall paths, and a keeper stage. The speed is enhanced by executing four clocked transistors together with a transition condition technique. The simulation result confirms that the proposed topology consumes the lowest amounts of power of 30.1997 and 22.7071 nW for parallel in –parallel out (PIPO) and serial in –serial out (SISO) shift register respectively covering 22 µm2 chip area. The overall design consist of only 16 transistors and is simulated in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology with a 1.2 V power supply.

https://www.mdpi.com/2079-9292/5/4/92/pdf

Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for a Cryptographic RFID Tag

Advances in active inductor based CMOS band-pass filter

Comparator plays an important role in overall performance of analog to digital converters (ADC) in all modern electronic devices used in handheld to industrial applications. High-speed devices with low voltage and low power are considered essential nowadays. This paper presents a CMOS based comparator design using 0.13 μm CMOS process in Mentor Graphics for ADC applications. The primary goal of this research work is to design high-speed and low power comparator using pre-amplifier latch circuit. The proposed design is powered by 1.2V supply and the output signal exhibits only 0.62ns delay which is very much competitive to the other researches. The comparator dissipates only 1.5nW power which is the lowest reported to date. The proposed design is highly compact occupying only 256 μm2 of silicon space. The proposed circuit will be highly useful for the electronic industries where low-power, high-performance, and compactness of devices are the crucial concerns.

Mohammad Torikul Islam Badal

Papers

Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for a Cryptographic RFID Tag

Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process

Advances in active inductor based CMOS band-pass filter

Design of a low-power high-speed comparator in 0.13μm CMOS