Field-programmable gate arrays (FPGAs) have recently evolved as a valuable component of the heterogeneous computing. The register transfer level (RTL) design flows demand the designers to be experienced in hardware, resulting in a possible failure of time-to-market. High-level synthesis (HLS) permits designers to work at a higher level of abstraction through synthesizing high-level language programs to RTL descriptions. This provides a promising approach to solve these problems. However, the performance of HLS tools still has limitations. For example, designers remain exposed to various aspects of hardware design, development cycles are still time consuming, and the quality of results (QoR) of HLS tools is far behind that of RTL flows. In this paper, we survey the literature published since 2014 focusing on the performance optimization of HLS tools. Compared with previous work, we extend the scope of the performance of HLS tools, and present a set of three-level evaluation criteria, covering from ease of use of the HLS tools to promotion on specific metrics of QoR. We also propose performance evaluation equations for describing the relation between the performance optimization and the QoR. We find that it needs more efforts on the ease of use for efficient HLS tools. We suggest that it is better to draw an analogy between the HLS development process and the embedded system design process, and to provide more elastic HLS methodology which integrates FPGAs virtual machines.

A Survey on Performance Optimization of High-Level Synthesis Tools

Technology scaling has exacerbated the aging impact on the performance and reliability of integrated circuits. By entering into nanotechnology era in recent years, the power density per unit of area has increased, which leads to a higher chip temperature. Aging in a chip is originated from multiple phenomena; all of them are intensified by increased temperature. Several circuit- and architecture-level schemes tried to mitigate the aging in the literature. However, these schemes are not sufficient for multi-core systems due to their unawareness of the unique constraints and features of these platforms. In this paper, we propose a system-level aging mitigation method, so-called Adaptive Task Allocation for Aging Reduction in Multi-core Embedded Real-time Systems (TAMER). As a task allocation algorithm, TAMER takes the cores’ utilization and their internal units’ activity into account to smooth the temperature pattern inside the chip. By minimizing both temporal and spatial thermal variations, TAMER prevents the occurrence of hotspot over time and space. We evaluated the TAMER method using a framework consisting of gem5 full-system cycle-accurate simulator, MATLAB, ESESC multi-core simulator, and HotSpot temperature modeling tool. The simulation results show that TAMER decreases the maximum and average temperature standard deviation of the cores by 56% and 37%, respectively, compared to the best previous temperature distribution task allocation algorithm. It is worth mentioning that, neither area nor performance overhead has been imposed on the system after the aforementioned improvements.

TAMER: an adaptive task allocation method for aging reduction in multi-core embedded real-time systems

Mixed-criticality cyber physical system provides great advantages in terms of cost, dependability, scalability and competitiveness. However, especially due to shared resources, the certification of these kind of systems is still challenging. Furthermore if the power management is integrated in the system, compliance with safety and security is even more complex. This paper presents the safety concept of a railway signalling use-case, considering a mixed-criticality object controller which includes a power management approach. The paper presents a proposal of using degraded modes and a safety/security analysis of low power techniques. The concept has been positively assessed by an independent certification body.

A railway safety and security concept for low-power mixed-criticality systems

Different strategies for the combination of merging and splitting transformation procedures for incompletely specified finite state machines implemented on field-programmable logic devices are offered. In these methods, such optimization criteria as the speed of operation, power consumption and implementation cost are considered already in the early phase of finite state machine synthesis. The methods also take into account the technological features of programmable logic devices and the state assignment method. The transformation quality ratio is calculated on the base of estimations of consumed power, critical path delay and number of utilized logic cells. The user is also able to choose the order of merging and splitting procedures and the direction of the optimization by setting weights for each criterion. The methods of the estimation of optimization criteria values are described, and the experimental results are also discussed.

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State Merging and Splitting Strategies for Finite State Machines Implemented in FPGA

Formal techniques for the functional verification of System-on-Chip (SoC) hardware have matured significantly over the last years. They can penetrate deeply into a design to exhibit complex functional dependencies between various design components in terms of detailed logical and temporal relationships. They can also provide a well-defined formal relationship between an abstract system model of a design and its concrete implementation at the register-transfer level (RTL). This paper shows how such knowledge available from formal verification can be “condensed” into a database that stores all registers and flip-flops, at which time points they are actually relevant for the correct behavior of the design and when they are not. We show that the comprehensive information on temporary unobservabilities in the design can be of great value to reach two nonfunctional design goals that play a dominant role in many design flows: safety and low power consumption. This paper presents techniques to assess the effects of soft errors by single-event upsets (SEUs) with formal precision and to relate the results of the proposed analysis to an abstract system model. For example, our analysis can determine which soft errors may lead to a system “crash” and which are guaranteed not to cause any harm. For the application of the proposed approach in power optimization, this paper presents techniques for clock gating and power gating. For the examined designs, we observe a reduction of power consumption between 10% and 50% on top of the state-of-the-art commercial power synthesis.

Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design Flows

Nowadays, power is a primary concern in digital circuits and clock distribution networks are particularly a significant power consumer. Therefore, clock gating is an effective technique in saving dynamic power by reducing the switching activities. In this paper, we propose a centralized and fine-grained microarchitecture-level clock gating for low power hardware accelerators which are automatically designed by high-level synthesis (HLS) tool. The basic principium of our idea is not to use any extra computation for generating clock enabled signals and exploit exiting signals of finite state machine for controlling the datapath clock network. After determining the current state in finite state machine, clock sub-tree of current state is enabled and the other sub-trees are disabled with a slight increase in circuit area. Our approach is implemented within an HLS design flow for automatic low power hardware accelerator generation in application specific integrated circuit design. Experimental results are obtained on a set of representative benchmark programs. Depending on the circuit size and number of registers, it is shown that 47%–86% reduction in power dissipation is observed.

Power Efficient High-Level Synthesis by Centralized and Fine-Grained Clock Gating

CMOS miniaturization and timing faults due to factors, such as aging, emphasize that embedded processor reliability is a major concern. Among the various aging mechanisms, negative bias temperature instability (NBTI) is encountered as the dominant factor. Techniques against NBTI are mostly based on aggressive $V_{\text {dd}}$ scaling, decelerating aging at the expense of performance degradation. Traditionally, designers use conservative guard-bands to combat timing faults, leading to loss of efficiency. Some other reactive approaches use sensors, requiring hardware modification and large area and debug overheads. According to the literature, two opportunities exist to compensate for the performance loss: instruction timing slacks imposed by static timing analysis (STA) and application computational error resiliency. This article proposes an efficient estimation model for the instruction-level timing slack probability distribution function (PDF) and gives a dynamic approach for statistical timing analysis, which is used for dynamic frequency management to improve performance of both error-resilient and error-sensitive applications. To this aim, we introduce a metric called architecture timing-fault vulnerability factor, considering NBTI and $V_{\text {dd}}$ effects. Simulation results show that the proposed timing slack PDF estimation model has an accuracy of about 94%, which can be used to increase throughput of error-resilient applications up to 3.2 times compared with when the traditional STA is used.

Aging-Aware Instruction-Level Statistical Dynamic Timing Analysis for Embedded Processors

In this paper, we present a free and open source toolchain that can be used for enumerating all custom instructions from C and C++ codes considering not only general constraints like circular dependencies but also parameterized architectural constraints such as number of read and write ports, area, and delay parameters and constraints. After enumerating all custom instructions, the toolchain can select the best subset of custom instructions for implementation.

Mostafa Ersali Salehi Nasab

Papers

Power Efficient High-Level Synthesis by Centralized and Fine-Grained Clock Gating

Aging-Aware Instruction-Level Statistical Dynamic Timing Analysis for Embedded Processors

UTIC: A toolchain for enumeration and selection of custom instructions