The present invention provides methods for fabricating semiconductor structures and devices, particularly ultra-shallow doped semiconductor structures exhibiting low electrical resistance. Methods of the present invention use modification of the composition of semiconductor surfaces to allow fabrication of a doped semiconductor structure having a selected dopant concentration depth profile, which provides useful junctions and other device components in microelectronic and nanoelectronic devices, such as transistors in high density integrated circuits. Surface modification in the present invention also allows for control of the concentration and depth profile of defects, such as interstitials and vacancies, in undersaturated semiconductor materials.

Methods for controlling dopant concentration and activation in semiconductor structures

Described herein are processing conditions, techniques, and methods for preparation of ultra-shallow semiconductor junctions. Methods described herein utilize semiconductor surface processing or modification to limit the extent of dopant diffusion under annealing conditions (e.g. temperature ramp rates between 100 and 5000° C./second) previously thought impractical for the preparation of ultra-shallow semiconductor junctions. Also described herein are techniques for preparation of ultra-shallow semiconductor junctions utilizing the presence of a solid interface for control of dopant diffusion and activation.

Preparation of ultra-shallow semiconductor junctions using intermediate temperature ramp rates and solid interfaces for defect engineering

The present invention provides methods for controlling defects in materials, including point defects, such as interstitials and vacancies, and extended defects, including dislocations and clusters. Defect control provided by the present invention allows for fabrication and processing of materials and/or structures having a selected abundance, spatial distribution and/or concentration depth profile of one or more types of defects in a material, such as vacancies and/or interstitials in a crystalline material. Methods of the invention are useful for processing materials by controlling defects to access beneficial physical, optical, chemical and/or electronic properties.

Defect engineering in metal oxides via surfaces

Impurity ions implanted into a semiconductor silicon substrate are not redistributed during a heating of the substrate from the substrate to the film. Such redistribution does not occur due to the direct nitridation of the silicon substrate for forming the silicon nitride film.

Process for producing a semiconductor device including an ion implantation step in combination with direct thermal nitridation of the silicon substrate

A silicon wafer having a tungsten and/or molybdenum film formed on its surface is heat-treated in hydrogen containing water vapor. Thus, silicon can be selectively oxidized without substantially oxidizing tungsten and/or molybdenum.

Method of producing semiconductor device

An improved insulated gate field effect transistor is achieved by using a material such as silicon nitride as an ion implantation and oxidation mask overlying a channel region, forming source and drain regions or extensions thereof by implanting ions of a conductivity modifier into a semiconductor substrate, and subjecting the implanted ions to a drive-in diffusion whereby the conductivity modifier ions are redistributed. The ion implantation allows greater control over the amount of conductivity modifier implanted in the lightly doped source and drain regions, the more uniform distribution of conductivity modifier increases the source-drain breakdown voltage, while the use of the silicon nitride mask provides simultaneously for general alignment of the channel region with the effective gate length.

Murray Arthur Polinsky

Papers

Method of making an insulated gate field effect transistor