The inter-chip communication system transfers signals across chip boundaries only when the signals change value. Thus no signals are wasted and every event signal has a fair chance of achieving communication across the boundary. The system includes a series of event detectors (3062, 3063, 3064) that detect changes in signal values and packet schedulers (3036, 3037, 3038) which can then schedule the transfer of these changed signal values to another designated chip. Working with a plurality of signal groups that represents signals at the separated connections, the event detectors (3062, 3063, 3064) detect events or changes in the signal values. When an event ro signal change has been detected, the event detector alerts the packet scheduler (3036, 3037, 3038). The packet scheduler employs a token ring scheme. When the scheduler receives a token and detects an event, the packet scheduler grabs the token and schedules the transmission of this packet in the next packet cycle. If, however, the packet scheduler receives the token but does not detect and event, it will pass the token to the next scheduler. At the end of each packet cycle, the packet scheduler that grabbed the token will pass the token to the next logic associated with another packet.

Inter-chip communication system

A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.

Adaptive power control

The scatter-gather technique is a commonly implemented approach to prevent cache-based timing attacks. In this paper we show that scatter-gather is not constant time. We implement a cache timing attack against the scatter-gather implementation used in the modular exponentiation routine in OpenSSL version 1.0.2f. Our attack exploits cache-bank conflicts on the Sandy Bridge microarchitecture. We have tested the attack on an Intel Xeon E5-2430 processor. For 4096-bit RSA our attack can fully recover the private key after observing 16,000 decryptions.

/pdf/cachebleed-a-timing-attack-on-openssl-constant-time-rsa-3ghy9pjbrg.pdf

CacheBleed: a timing attack on OpenSSL constant-time RSA

A system and method are provided for processing storage commands between a host and a target. The system includes a first line card, a system card, and a second line card. The storage command that is issued from the host is received by the first line card. The first line card determines whether or not it can process the request by itself and, if so, forwards the storage command to the second line card for forwarding (and eventual processing) by the target. If the first line card cannot process the storage command by itself, it forwards the storage command to the system card for additional processing. The revised storage command is issued from the system card to the first line card. The first line card then issues the revised storage command to the second line card for eventual processing by the target.

System and method for scalable switch fabric for computer network

A cache system and method in accordance with the invention includes a cache near the target devices and another cache at the requesting host side so that the data traffic across the computer network is reduced. A cache updating and invalidation method are described.

Caching system and method for a network storage system

An interleaved cache is used for multiple data accesses per clock in a microprocessor. The cache includes a storage array having multiple banks of single-ported memory cells for storing data, a bank selector for selecting banks in the storage array simultaneously according to the multiple data accesses, and a datapath for transfering data between execution units in the microprocessor and the storage array. The cache of the present invention also includes contention logic for prioritizing the multiple data accesses when multiple data accesses are to be same bank.

Interleaved cache for multiple accesses per clock cycle in a microprocessor

A processor (100) has a clock generator (102), a sleep pin that receives an external sleep signal, and a first interface circuit (104) coupled to the clock generator circuit (102) and the sleep pin The clock generator circuit (102) generates a core clock signal (116) and a bus clock signal (118) in response to an external clock signal (122) When the external sleep signal is asserted, the processor (100) enters a sleep state when the core clock signal (116) and the bus clock signal (118) are in a first predetermined relationship with each other

Processor with sleep and deep sleep modes

A processor capable of selecting between a write-back and a write-through mode of operation includes a bus interface unit for transferring information across the external bus. A local cache memory is coupled to the bus interface unit for storing information received from the bus interface unit. The processor also includes a control unit coupled to the cache memory and the bus interface unit. The control unit is operable to restart an interrupted operation from a point of interruption. A storage device coupled to the control unit stores a value corresponding to the point of interruption of the operation.

Method and apparatus for selecting a mode for updating external memory

A microprocessor instruction for performing an in-place byte swap on 32-bit data type to convert data stored in a big-endian memory format to a little-endian memory format, or visa-versa, is described. The invention comprises a modified barrel shifter which includes a plurality of multiplexers for selectively coupling data from one or more input buses to an output bus. The coupling of the individual bit lines of the data buses is arranged such that the lower order bits of the 32-bit quantity are exchanged with the higher order bits and visa-versa. Control lines connected to each of the multiplexers provide a means for controlling the byte swapping operation.

Apparatus and method for swapping the byte order of a data item to effectuate memory format conversion

A cache memory is provided with a plurality of address ports and a corresponding plurality of tag ports for use with multiple pipes in a pipelined system. One of the address ports is dedicated to snooping and the remaining address ports provide concurrent access to the cache for references to one or more independent addresses respectively issued by one or more pipes. A tag port is provided for each of the address ports to provide concurrent hit/miss status for each address.

Mustafiz R. Choudhury

Papers

Interleaved cache for multiple accesses per clock cycle in a microprocessor

Processor with sleep and deep sleep modes

Method and apparatus for selecting a mode for updating external memory

Apparatus and method for swapping the byte order of a data item to effectuate memory format conversion

Multiported cache and systems