A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.

Method for design optimization using logical and physical information

In this era of Deep Sub-Micron (DSM) technologies, the impact of interconnects is becoming increasingly important as it relates to integrated circuit (IC) functionality and performance. In the traditional top-down IC design flow, interconnect effects are first taken into account during logic synthesis by way of wireload models. However, for technologies of 0.25 /spl mu/m and below, the wiring capacitance dominates the gate capacitance and the delay estimation based on fanout and design legacy statistics can be highly inaccurate. In addition, logic block size is no longer dictated solely by total cell area, and is often limited by wiring area resources. For these reasons, wiring congestion is an extremely important design factor, and should be taken into consideration at the earliest possible stages of the design flow. In this paper we propose a novel methodology to incorporate congestion minimization within logic synthesis, and present results for industrial circuits that validate our approach.

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Congestion-Aware Logic Synthesis

Traditionally, interconnect effects are taken into account duringlogic synthesis via wireload models, but their ineffectiveness forDSM technologies has been demonstrated and various physicalsynthesis approaches have been spawned to address the problem. Ofparticular interest is that logic block size is no longer dictatedexclusively by total cell area, yet synthesis optimizationobjectives are aimed specifically at minimizing the number and sizeof cells. Methodologies that incorporate congestion within thelogic synthesis objective function have been proposed in[9][10][11] and [15]; however, as we will demonstrate, predictingthe true congestion prior to layout is not possible, and theefficacy of any approach can only be evaluated after routing iscompleted within the fixed die size. In this paper we propose apractical, complete methodology which first performscongestion-aware technology mapping using a global weighting factorfor the cost function [15], and then applies incremental localizedunmapping and remapping on congested areas. This complete approachaddresses the problem that one global factor is not ideally suitedfor all regions of the designs. Most importantly, through theapplication of this methodology to industrial examples we will showthat any attempt at a purely top-down single-pass congestion-awaretechnology mapping is merely wishful thinking.

/pdf/understanding-and-addressing-the-impact-of-wiring-congestion-5b8j1plhyc.pdf

Understanding and addressing the impact of wiring congestion during technology mapping

The authors examine the problem of mapping a Boolean network using gates from a finite size cell library to minimize the total gate area subject to constraints on signal arrival time at the primary outputs. The approach consists of two steps: In the first step, delay functions are computed at all nodes in the network, and in the second step the mapping solution is generated based on the computed delay functions and the required times at the primary outputs. For a NAND-decomposed tree, subject to load calculation errors, this two step approach finds the minimum area mapping satisfying all delay constraints if such a solution exists. The algorithm has polynomial run time on a node-balanced tree and is easily extended to mapping a directed acyclic graph. The results compared favorably with those of the MIS2.2 mapper. >

A near optimal algorithm for technology mapping minimizing area under delay constraints

In this paper we present a placement-intelligent resynthesis methodology and optimization algorithms to meet post-layout timing constraints while at the same time reducing the interconnect congestion. We begin with the synthesized design netlist after initial placement and make incremental modifications - taking placement into account - to generate a final netlist and placement that meets the delay constraints after place and route. The algorithms described have been implemented as part of a tool for placement based resynthesis. The tool has been used with a number of pre-optimized designs from industry and to obtain improvements in post-placement delays ranging from 13 to 22% with improved routability.

/pdf/a-methodology-and-algorithms-for-post-placement-delay-3bo1rzsxx5.pdf

A Methodology and Algorithms for Post-Placement Delay Optimization

The authors present techniques to integrate interconnection optimization with logic restructuring and technology decomposition phases of logic synthesis. The approach is based on a point placement of a Boolean network which is used to guide the synthesis process by providing accurate estimates on wiring area and delay. The placement solution is incrementally updated as intermediate Boolean nodes are extracted or eliminated during the decomposition or elimination procedures. Combining these techniques with layout-driven technology mapping makes it possible to produce a synthesis solution and a 'companion' placement solution for a given combinational logic circuit simultaneously. Using these techniques, circuits with smaller area and higher performance can be generated. >

/pdf/layout-driven-logic-restructuring-decomposition-4ngj1zlgdv.pdf

N. Bhat

Papers

Layout driven logic restructuring/decomposition