This is an introduction to the Classic Paper on MOSFET scaling by R. Dennard et al., Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions,' published in the IEEE Journal of Solid-State Circuits in October 1974. The history of scaling and its application to very large scale integration (VLSI) MOSFET technology is traced from 1970 to 1998. The role of scaling in the profound improvements in power delay product over the last three decades is analyzed in basic terms.

/pdf/mosfet-scaling-the-driver-of-vlsi-technology-1izpifmnsl.pdf

Mosfet Scaling-the Driver of VLSI Technology

Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.

Semiconductor devices with non-punch-through semiconductor channels having enhanced conduction and methods of making

A qualitative and quantitative analysis of the deep depletion MOSFET operated in the regimes of depletion, enhancement and depletion/enhancement, is presented The quantitative analysis presented here does not make any of the simplifications made in some earlier papers, applicable to shallow channel depletion MOSFETs, and uses a four terminal device model so as to provide a complete set of characterisation equations for each mode of operation It is demonstrated that the device parameters of flatband voltage, implanted channel doping and depth, and bulk and surface carrier mobilities, can easily be determined by use of some of the characteristics equations in conjunction with simple measurements made directly from the drain current/drain voltage characteristics Furthermore these parameters are applicable to bulk-channel charge-coupled devices fabricated under the same implantation and drive-in conditions As the device parameters are determined from the drain current/drain voltage characteristics the techniques presented offer an attractive alternative to the more complicated C-V methods used for bulk-channel charge-coupled device characterisation The validity of the model and the techniques used to determine the device parameters is demonstrated by the good agreement between calculated and measured results obtained from fabricated devices

Analysis of the deep depletion MOSFET and the use of the d.c. characteristics for determining bulk-channel charge-coupled device parameters

n-channel enhancement/depletion technology and circuits are described. The threshold voltage adjustment to form the enhancement- and depletion-mode devices are achieved by ion implantation. This allows optimization of the performance and circuit density. The calculated and experimentally observed speed-power product is 10 pJ/pF with a single +5-V power supply. Inversion of the field region on the high resistivity p-type substrate is completely eliminated by the use of an implanted field shield.

http://ieeexplore.ieee.org/iel5/4/22530/01050379.pdf

n-Channel Ion-Implanted Enhancement/Depletion FET Circuit

n-channel ion-implanted enhancement/depletion FET circuit and fabrication technology

A design approach of the depletion-load inverter is given in which an attempt is made to obtain large noise margins. It is predicted that the circuit will operate with a 10-15 pJ/pF power- delay product at +5-V supply voltage. Some experimental integrated circuits were designed and fabricated by making use of a novel n-channel MOS technology that utilizes both enhancement and depletion-type MOSFET on a chip. A fully decoded transistor- transistor logic (TTL)-compatible READ-ONLY memory was fabricated, resulting in 300 ns total access time at a +5-V single power supply.

N. Hashimoto

Papers

A high-performance N-channel MOS-LSI using depletion-type load elements

"A short-channel, punch-through-breakdown-free MOS transistor"

Technology and Performance of N-channel MOS-LSI Using Depletion-Type Load Elements