A set of 0.8 mu m CMOS VLSIs developed for shared buffer switches in asynchronous transfer mode (ATM) switching systems is described. A 32*32 unit switch consists of eight buffer memory VLSIs, two memory control VLSIs, and two commercially available first in first out (FIFO) memory LSIs. Using the VLSIs, the switch can be mounted on a printed board. To provide excellent traffic characteristics not only under random traffic conditions but also under burst traffic conditions, this switch has a 2-Mb shared buffer memory, the largest reported to date. which can save 4096 cells among 32 output ports. This switch has a priority control function to meet the different cell loss rate requirements and switching delay requirements of different service classes. A multicast function and a 600 Mb/s link switch architecture, which are suitable for ATM network systems connecting various media, and an expansion method using the 32*32 switching board to achieve large-scale switching systems such as 256*256 or 1024*1024 switches are discussed. >

32*32 shared buffer type ATM switch VLSIs for B-ISDNs

Apparatus, and accompanying methods for use therein, for a large (e.g. approximately 1 Terabit/second), fault tolerant packet switch (200), particularly suited for asynchronous mode transfer (ATM) communication, which utilizes cell address look-ahead in conjunction with parallel planes of self-routing cross-points (550), staggered time phased contention resolution and shared memory based input and output modules (260 and 270, respectively). Each incoming packet cell has added thereto an additional header field containing information identifying a particular output module and a particular output port of that module. An input module associated with the switching crosspoints changes the additional header information to identify the particular output module of the next subsequent packet cell.

Packet address look-ahead technique for use in implementing a high speed packet switch

An asynchronous transfer mode (ATM) switch architecture called a shared buffer memory switch whose output cell buffers are shared among all the output ports of the switch is proposed. Experimental measurements and a discussion about the traffic characteristics of the switch architecture are carried out to determine how much buffer memory will be reduced through buffer sharing under various traffic conditions and to roughly estimate how many buffers are needed for the switch to meet certain requirements. The resultant estimate shows that buffer sharing reduces the necessary buffer memory to less than 1/5 of what would otherwise be required, and the required buffer size is about 128 cells/output for a 32*32 switch when considering bursty traffic conditions. LSI implementation is also discussed to show that a 32*32 switch can be composed of about 12 chips mounted on one printed board. >

Shared buffer memory switch for an ATM exchange

Apparatus, and accompanying methods for use therein, for a large (e.g. approximately 1 Terabit/second), fault tolerant packet switch (200), particularly suited for asynchronous mode transfer (ATM) communication, which utilizes cell address look-ahead in conjunction with parallel planes of self-routing cross-points (550), staggered time phased contention resolution and shared memory based input and output modules (260 and 270, respectively). An ATM cell applied to an input port of an interface module contains a data field and a virtual channel identifier (VCI) field. The VCI is translated by the interface module into a new VCI, to identify an output of the virtual channel for the switch and appends to the cell an additional routing header which will be used strictly for internal use in routing the entire cell through the switch and which includes distinct first and second portions.

Large fault tolerant packet switch particularly suited for asynchronous transfer mode (ATM) communication

This paper discusses the configuration of an ATM(Asynchronous Transfer Mode) switching network with a shared buffer memory switch (SBMS) which has the potential to provide good traffic characteristics and easy LSI implementation. The scaling factors of the ATM switching network under a condition of mixed applications are discussed first. Then the SBMS as the unit element ofthe multi-stage switching network is described, and its performance evaluation and experimental data are introduced. The data indicate excellent performance under burst cell arrival condition. Last a concept of a large scale ATM switching network configuration with multi-stage switches is proposed. The non blocking condition in ATM multi-stage switching network as an alternative resource management scheme is described.

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Papers

Large scale atm multi-stage switching network with shared buffer memory switches