A method of manufacturing a semiconductor chip package. A sacrificial layer is used as a base to selectively form an array of conductive pads such that a central region is defined by the pads. A back surface of a semiconductor chip is next attached to the sacrificial layer within the central region between the pads so that the contact bearing surface of the chip faces away from the sacrificial layer. The chip contacts are then electrically connected to respective pads, typically by wire bonding a wire therebetween. A curable, dielectric liquid encapsulant is then deposited on the sacrificial layer such that the pads, electrical connections and chip are fully encapsulated, as by an overmolding operation. The encapsulant is then cured and the sacrificial layer is either completely removed or is selectively removed to expose a surface of the pads for electrical attachment to a PWB and the back surface of the chip for creating a direct thermal path from the chip to the PWB.

Methods for manufacturing a semiconductor package having a sacrificial layer

System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and high-performance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two- and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. High-density wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a "virtual chip" using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electro-optic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

An electrical resistor is made by providing a sacrificial layer and conductive pads disposed on a first surface of the sacrificial layer. An electrically resistive material is deposited over the pads and on the first surface of the sacrificial layer to form at least one unit including the resistive material and the pads. At least part of the sacrificial layer is then removed so as to expose one or more of the pads.

Methods for manufacturing resistors using a sacrificial layer

A method of forming high definition elements for electrical and electronic devices, substrates, and other components from or including viscous material. The method includes inverting the electrical components after the viscous material is applied and maintaining the inverted orientation until the viscous material dries or cures enough to maintain definition of its perimeter and edge characteristics.

Gravitationally-assisted control of spread of viscous material applied to semiconductor assembly components

Effect of Bonding Force on the Conducting Particle With Different Sizes

Transfer molding is a typical method for packaging integrated circuits (ICs). Transfer molding is very difficult to do at heights less than 1 mm, and has a limited surface mounting area. Recent research of high density surface mounting for thinner and lighter weight packaging has progressed for both IC cards and liquid crystal displays (LCDs). However, the dispensing method has many problems, such as the height variations of the coating, difficulties of uniform spreading on large size ICs, and one-by-one encapsulation. A unique printing method is developed to solve such problems. Through this method it is possible to achieve a height less than 1 mm and a uniform thickness on an integrated system. On reaching these parameters, the surface mount ICs replace molded packaged devices that are manufactured using expensive equipment and molding dies. The method requires only a small amount of epoxy resin and is, therefore, more economical than the conventional transfer molding process. A one-component epoxy resin NPR-150 suitable for printing is developed. >

New packaging of a chip on a board by a unique printing method

A novel printing method which has been found to be successful in making the chip-on-board (COB) packaging for ICs has been developed. Using this technique, it has become possible to achieve less than mm height, uniform thickness, and all-in-one operation. This method is more economical than the transfer-molding method. In addition, the cost of packages is much reduced, and it is more suited to mass production. One-component epoxy-resin, called NPR-150, has been developed which is suitable for printing. Deformation of gold wires was not observed, and reliability test results showed excellent levels, comparable to the formal transfer-molding packaging. >

http://ieeexplore.ieee.org/iel2/543/4250/00163977.pdf

New packaging of chip-on-board by unique printing method

Extensive study of methods to screen print an encapsulant on bare die for multichip modules (MCM) and chip-on-board (COB), TAB, and flip-chip applications has produced a "printing encapsulation system" (PES). The key to this system was in the development of a liquid epoxy resin with optimum properties for printing encapsulation. We have developed a printing encapsulation system (PES) that produces high reliability and high quality encapsulated components, free of voids and demonstrating optimal thin consistent encapsulated shapes for advanced COB applications. The PES utilizes an epoxy resin we created with viscosity and open lid storage properties appropriate for mass production. The thixotropic properties have been adjusted carefully to allow for consistent high volume results. The system yields a void free encapsulated device that a is resistant to thermal shock and moisture after short cure times. Full curing can be achieved in as short as 15 min, lending this material and process easily to in-line manufacturing. >

Printing encapsulation systems (PES) of advanced multichip module and COB device

Flip-chip technology has been rapidly progressing in the laboratory. But industrial use of flip-chip has not progressed satisfactorily. Packaging materials are using low viscosity liquid type underfill epoxy resin, and packaging methods are using dispenser systems. These systems have many problems in mass production as follows. (1) This process needs to underfill epoxy resin many times. (2) This epoxy resin must use low viscosity epoxy resin to underfill under LSI, and it can't contain much filler. It is difficult to get low expansion epoxy resin system. Delamination between LSI and underfill epoxy resin sometimes occurs. We solved these problems using our PES process and PES epoxy resin. At the first step, we developed new type underfill epoxy resin. This epoxy resins has low expansion, high purity, high adhesive strength, high Tg, high humidity resistance and high electric resistance. This underfill epoxy resin didn't have mismatching between LSI and board. At the secondary step, we developed the special PES for underfill method of flip-chip. We can get no bubble process for underfill packaging of flip-chip. This process is formed of flip-chip bumping/spl rarr/PES printing/spl rarr/vacuum process/spl rarr/heat curing/spl rarr/test. This process is very simple and underfills many LSI chips at once.

Flip-chip packaging using PES (Printing Encapsulation Systems) and PES underfill epoxy resin

MCM/sup L/ can expect to be the main current of semiconductor packaging technology in near future. BGA, PLCC and PGA packaging methods will expect much of this application. But the most pressing problem is warp after the packaging process. The warp after packaging needs to be below 150 /spl mu/m at BGA and 100 /spl mu/m at PLCC. We have already developed the Printing Encapsulation Systems (PES). PES is able to make low cost and mass produced semiconductor packaging. This paper describes the use of PES to make MCM/sup L/ semiconductor packaging. We have developed a low warp packaging epoxy resin using elastomer modified epoxy resin to fit BGA, PLCC and PGA. We verified the low stress epoxy resin using dynamic mechanical properties and internal stress measurements. We packaged BGA, PLCC and BGA with this low stress epoxy resin using PES, and measured the warp of each packaging. We obtained good results for the warp, demonstrating that using this low stress epoxy resin and PES, low cost and high reliability packaging of BGA, PLCC and PGA could be achieved. >

N. Oyama

Papers

New packaging of a chip on a board by a unique printing method

New packaging of chip-on-board by unique printing method

Printing encapsulation systems (PES) of advanced multichip module and COB device

Flip-chip packaging using PES (Printing Encapsulation Systems) and PES underfill epoxy resin

High reliability MCM packaging using low stress liquid type epoxy resin by printing encapsulation systems (PES)