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N. Seifert
Researcher at Intel
Publications - 44
Citations - 2534
N. Seifert is an academic researcher from Intel. The author has contributed to research in topics: Soft error & Combinational logic. The author has an hindex of 22, co-authored 44 publications receiving 2412 citations.
Papers
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Journal ArticleDOI
Robust system design with built-in soft-error resilience
TL;DR: A new design paradigm reuses design-for-testability and debug resources to eliminate transient errors caused by terrestrial radiation in chip designs.
Journal ArticleDOI
Sequential Element Design With Built-In Soft Error Resilience
Ming Zhang,Subhasish Mitra,Tak M. Mak,N. Seifert,N.J. Wang,Quan Shi,Kee Sup Kim,Naresh R. Shanbhag,Sanjay J. Patel +8 more
TL;DR: The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design- for-testability and design-for-debug resources to minimize area overheads.
Proceedings ArticleDOI
Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices
N. Seifert,P. Slankard,M. Kirsch,B. Narasimham,Victor Zia,C. Brookreson,A. Vo,Subhasish Mitra,B. Gill,Jose A. Maiz +9 more
TL;DR: This work provides a comprehensive summary of radiation-induced soft error rate (SER) scaling trends of key CMOS bulk devices and a novel methodology to extract one-dimensional cross sections of the collected charge distributions from measured multi-bit statistics is introduced.
Journal ArticleDOI
Soft Error Susceptibilities of 22 nm Tri-Gate Devices
N. Seifert,B. Gill,Shah M. Jahinuzzaman,Joseph M. Basile,V. Ambrose,Quan Shi,Randy Allmon,A. Bramnik +7 more
TL;DR: In this paper, measured radiation-induced soft error rates (SER) of memory and logic devices built in a 22 nm high-k metal gate bulk Tri-Gate technology are reported. But, the results demonstrate excellent single event upset (SEU) scaling benefits of tri-gate devices.
Proceedings ArticleDOI
Combinational Logic Soft Error Correction
TL;DR: Two techniques for correcting radiation-induced soft errors in combinational logic are presented - error correction using duplication, and error Correction using time-shifted outputs.