A process is disclosed for fabricating LDD CMOS structures having a reduced mask count and improved manufacturability. In one embodiment of the invention a CMOS structure is formed having gate insulators overlying N and P type surface regions. Gate electrodes are formed on each of the surface regions and a spacer forming material is deposited over the electrodes and the surface regions. The spacer material is anisotropically etched from one of the surface regions to form spacers at the edge of the first gate electrode while retaining the spacer forming material over the second surface region. Source and drain regions of the first MOS transistor are implanted using the spacers as an implantation mask. The spacers are removed and a lightly doped source and drain is implanted using the gate electrode as a mask. The implanted source and drain regions are oxidized using the remaining spacer forming material as an oxidation mask to prevent oxidation of the second surface region. Devices are then fabricated in that second surface region by implanting devices of opposite conductivity type either with or without the formation of spacers and an LDD structure on the devices of second conductivity type.

LDD CMOS process

The present invention features soft tissue implants and methods for making same The implants can include a biocompatible film (14) that is rendered porous due to the inclusion of uniformly or non-uniformly patterned cells (22), and the film has a thickness of less than about 0015 inches in the event the starting material is non-porous and less than about 0035 inches in the event that starting material is a microporous film Multi-film implants can also be made

Soft tissue implants and methods for making same

In a method for fabricating an MOS structure, in accordance with one embodiment, a layer of material that serves as an etching stop during the side wall spacer etch, is inserted between the silicon substrate and the side wall spacer. In another embodiment of the invention, after establishing differential layer thicknesses on the source/drain surface, the side wall spacer is completely removed and light and heavy ion implantation steps are performed sequentially with one single lithographic step. In a further embodiment of the invention, after the self-aligned silicide is formed, the side wall spacer is removed, and light and heavy ion implantation steps are sequentially performed.

Process for fabricating self-aligned silicide lightly doped drain MOS devices

An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly doped junction is aligned with the central alignment members and a heavily doped junction is aligned with the outboard alignment members.

Double implanted LDD transistor self-aligned with gate

To provide a highly reliable semiconductor device which does not suffer from a crack in its package, a semiconductor chip 12 is mounted on a lead frame 11 with a bonding layer 13 between them, and they are sealed with a sealing resin 14. The lead frame 11 has a base member 11a essentially consisting of Cu and an oxide film 11b essentially consisting of an oxide of the base member 11a formed on the base member and having a thickness of about 50 nm or below. By controlling the oxide film 11b to a thickness of about 50 nm or below, an adhesion strength with the sealing resin 14 is improved greatly, so that a package crack does not occur even if a large thermal load is applied in a reflow process for mounting.

Semiconductor device, and manufacturing method of the same

A method for manufacturing a semiconductor device, capable of forming, with good controllability, impurity regions of a low impurity concentration, includes the steps of: forming a gate electrode on a surface of a semiconductor substrate through a gate oxide film; forming a first film on the surfaces of the gate electrode and the semiconductor substrate; forming a non-single-crystalline silicon film to cover the entire surface; forming a second film to cover the entire surface; performing anisotropic etching of the second film to form residual second films on the side walls of that step portion non-single-crystalline silicon film which is formed corresponding to a shape of the gate electrode; performing etching of the non-single-crystalline silicon film by using the residual second films as masks to form residual non-single-crystalline silicon films on the side walls of the gate electrode through the first film; ion-implanting an impurity having a conductivity type opposite to that of the semiconductor substrate by using as masks the gate electrode and the residual non-single-crystalline silicon films; removing the residual non-single-crystalline silicon films; and annealing a resultant structure to activate the impurity so as to form source and drain regions each of which comprises an impurity region of a high impurity concentration and an impurity region of a low impurity concentration which is adjacent to the impurity region of the high impurity concentration and which is located under a structure area corresponding to one of the removed non-single-crystalline silicon films.

Nagakubo Yoshihide

Papers

Method for manufacturing semiconductor device