Showing papers by "Navneet Gupta published in 2013"
05 Jan 2013
TL;DR: This paper demonstrates a power optimization technique using an accurate differential sensing latch called PODIA, and shows that power saving of up to 50% can be achieved in a 16 × 16 multiplier made using the proposed flip-flop.
Abstract: Deep sub micron designs are susceptible to huge variations, justifying the in-situ optimization of power consumption in SoCs and IPs. It is essential to scale voltage to the lowest possible value to get maximum power saving while ensuring correct operation. Accurate estimation of error rates is required to use recovery driven DVFS techniques such as slack optimization [1], [2]. Due to extra logic added for short path constraint, metastability, etc., desired accuracy level and a wider voltage scaling range is not achievable through conventional DVFS method, resulting in reduced power savings. This paper demonstrates a power optimization technique using an accurate differential sensing latch called PODIA. A typical safety margin of 200ps is achieved between the main flip-flop and shadow latch without any short path constraint. Metastability resilience is achieved while clocking is also simplified. A gain of 90ps to 30 ps with respect to the conventional RAZOR architecture [3] is achieved across the operating voltage range of 0.6 to 1V respectively. Self timed differential amplifier based latching is used to reduce power consumption by using early detection of data transition. It is shown through spice simulations that power saving of up to 50% (across Process, Voltage and Temperature corners) can be achieved in a 16 × 16 multiplier made using the proposed flip-flop.