A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for nicker (1/f) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator.

Phase noise and jitter in CMOS ring oscillators

In the paradigm of stochastic computing, arithmetic functions are computed on randomized bit streams. The method naturally and effectively tolerates very high clock skew. Exploiting this advantage, this paper introduces polysynchronous clocking, a design strategy in which clock domains are split at a very fine level. Each domain is synchronized by an inexpensive local clock. Alternatively, the skew requirements for a global clock distribution network can be relaxed. This allows for a higher working frequency and so lower latency. The benefits of both approaches are quantified. Polysynchronous clocking results in significant latency, area, and energy savings for wide variety of applications.

Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits

This paper presents the design of a low DC power, low phase noise single-ended ring oscillator (RO) in 0.18 μm CMOS technology. It introduces a new RO output phase control technique. This RO uses a voltage pull-down circuit to produce different output signal phases. The proposed RO employs the pulse injection (PI) technique for phase noise and spurious signals suppression. The proposed injection locked ring oscillator (ILRO) can be used for phase shift keying (PSK) implementation. The proposed ILRO has an oscillation frequency of 4.5 GHz with a fine tuning range of 540 MHz. It consumes only a 4.25 mW of power while having a phase noise of -130.9 dBc/Hz @ 1MHz offset. Through this ILRO design, a figure of merit (FoM) of -197.68 dBc/Hz has been achieved.

An eight-phase CMOS injection locked ring oscillator with low phase noise

This paper investigates the performance of array multipliers utilizing FinFET models for the following feature sizes: 20nm, 16nm, 14nm, 10nm and 7nm. Using basic array multiplier topology and standard cell 28 transistor full adders, the static power and delay of FinFET array multiplier circuits were investigated using HSPICE and low power Predictive Technology Models (PTM). Simulation results show an increase in static power and a decrease in delay as the feature size decreases. Comparisons between array multiplier sizes show nonlinear increases in both static power and delay as size increases from 4×4 up to 16×16. The results obtained in this research will provide a starting point for the design and analysis of more complex FinFET based arithmetic circuit designs.

http://ieeexplore.ieee.org/iel7/6900043/6908326/06908563.pdf

Leakage and delay analysis in FinFET array multiplier circuits

The power consumption of high performance integrated circuits has increased significantly with technology scaling. Higher power consumption shortens the battery lifetime of portable devices. Furthermore, the increased power consumption poses limitation on the continued technology scaling due to the associated higher power density. In this paper, the sources of power consumption are identified and modeled. Implementation of various techniques and the proposed technique for reducing total leakage current for low power SRAM cell is presented. It is observed in the paper that the total leakage current and power dissipation of the proposed technique is minimized to 52.89 fA and 4.75 nW respectively. Simulations have been performed on Cadence virtuoso 45 nm technologies.

Leakage current reduction in finfet based 6T SRAM cell for minimizing power dissipation in nanoscale memories

This paper represents the design and analysis of ring oscillator using cadence virtuoso tool in 45 nm technology. Ring oscillator consists of odd number of stages with feedback circuit which forms a closed loop in which each stage output depends on the previous stage. In this paper, nine stage ring oscillator have been designed with a capacitor of 1 fF at each stage and simulated for various parameters such as delay, noise, jitter and power consumption. Power consumption, jitter, noise have been reduced in nine stage ring oscillator. Periodic steady state response of ring oscillator is also observed. Power consumption is reduced by 18.9 %.

Design and analysis of CMOS ring oscillator using 45 nm technology

The conventional single-gate MOSFETs faces great challenges in scaling down of devices due to the severe short-channel effects that reason an exponential gain in the leakage current. To minimize the short channel effect Double-gate FinFET can be used in place of conventional MOSFET circuits because of the self-alignment of the two gates. Design of XOR and XNOR circuits is suggested to improve the speed and power of these circuits and is basic building block of many arithmetic circuits. This paper compares and evaluates the performance of various designs of pass transistor based XOR and XNOR circuits. This paper demonstrates comparative performance study of high speed, low power and low voltage on XOR and XNOR digital circuit. The performances of XOR and XNOR circuits are based on CADANCE VIRTUOSO tool at 45 nm by applying voltage supply 0.7 voltages and the temperate is 27°C. Simulation results reveal low power, delay, power, delay product (PDP), average dynamic power consumption, energy delay product (EDP).

Design and analysis of FINFET pass transistor based XOR and XNOR circuits at 45 nm technology

This paper demonstrates and evaluates comparative performance study of low power FINFET based various designs of XOR and XNOR circuits. The scaling of conventional CMOS circuit inclines towards the short channel effect on account of leakage current increase in the circuit. To minimize the short channel effect FINFET can be used in place of conventional CMOS circuits. This paper evaluates and compares the performance of   XOR and XNOR logic circuits. This comparison is based on analysis of various design techniques for XOR and XNOR logic circuits. The performances of XOR and XNOR circuits are based on CADANCE VIRTUOSO tool at voltage supply 0.7 voltages and the temperate is 27 0 C and and all the simulation results have been generated by Cadence SPECTRE simulator at 45nm technolog. The XOR and XNOR circuits with static circuit, transmission gate and with feedback transistors designs are desirable for arithmetic circuits. Simulation results reveal low power, delay, power, delay product (PDP), average dynamic power consumption.

Modelling and Performance Analysis of Various FinFET Based Design Techniques for XOR and XNOR Circuits at 45 Nanometer Regime

technology has scaled down, the implications of leakage current and power analysis for memory design have increased. To minimize the short channel effect Double-gate FinFET can be used in place of conventional MOSFET circuits due to the self-alignment of the two gates. Design for XOR and XNOR circuits is suggested to improve the speed and power. These circuits act as basic building blocks for many arithmetic circuits. This paper contrasts and evaluates the performance of conventional CMOS and FinFET based XOR-XNOR circuit design. It is based on the study of high speed, low power, and small area in XOR-XNOR digital circuits. The proposed FinFET based XOR and XNOR circuits have been designed using Cadence VIRTUOSO Tool applying voltage supply of 0.2 to 1.2 voltages, with temperature at 27 0 C and all the simulation results have been generated by Cadence SPECTRE simulator at 45nm technology. Simulation results exhibit low power, delay, power, delay product (PDP), and average dynamic power consumption.

/pdf/analysis-of-conventional-cmos-and-finfet-based-6-t-xor-xnor-3gzvfc4ny3.pdf

Neha Yadav

Papers

Design and analysis of CMOS ring oscillator using 45 nm technology

Design and analysis of FINFET pass transistor based XOR and XNOR circuits at 45 nm technology

Modelling and Performance Analysis of Various FinFET Based Design Techniques for XOR and XNOR Circuits at 45 Nanometer Regime

Analysis of Conventional CMOS and FinFET based 6-T XOR-XNOR Circuit at 45nm Technology

In-line and off-line NDT defect monitoring for thermoplastic automated tape layup