Alta Devices, Inc. has fabricated a thin-film GaAs device on a flexible substrate with an independently-confirmed solar energy conversion efficiency of 27.6%, under AM1.5G solar illumination at 1 sun intensity. This represents a new record for single-junction devices under non-concentrated sunlight. This surpasses the previous record, for conversion efficiency of a single-junction device under non-concentrated light, by more than 1%. This is due largely to the high open-circuit voltage (V oc ) of this device. The high V oc results from precise control of the dark current. The fact that this record result has been achieved with a thin-film shows that, for GaAs material systems, the majority of the growth substrate is not needed for device performance. This allows one to consider amortizing the potentially high cost of a GaAs growth substrate by growing a thin-film, lifting it off, and reusing the same substrate multiple times. This technology therefore has the potential to be a novel high-performance, thin-film option for terrestrial photovoltaics.

27.6% Conversion efficiency, a new record for single-junction solar cells under 1 sun illumination

Substituting the doped amorphous silicon films at the front of silicon heterojunction solar cells with wide-bandgap transition metal oxides can mitigate parasitic light absorption losses. This was recently proven by replacing p-type amorphous silicon with molybdenum oxide films. In this article, we evidence that annealing above 130 °C—often needed for the curing of printed metal contacts—detrimentally impacts hole collection of such devices. We circumvent this issue by using electrodeposited copper front metallization and demonstrate a silicon heterojunction solar cell with molybdenum oxide hole collector, featuring a fill factor value higher than 80% and certified energy conversion efficiency of 22.5%.

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22.5% efficient silicon heterojunction solar cell with molybdenum oxide hole collector

Solar cell efficiency tables (version 33)

In a solar cell having p doped regions and n doped regions alternately formed in a surface of a semiconductor wafer in offset levels through use of masking and etching techniques, metal contacts are made to the p regions and n regions by first forming a base layer contacting the p doped regions and n doped regions which functions as an antireflection layer, and then forming a barrier layer, such as titanium tungsten or chromium, and a conductive layer such as copper over the barrier layer. Preferably the conductive layer is a plating layer and the thickness thereof can be increased by plating.

Metal contact structure for solar cell and method of manufacture

A precursor composition for the deposition and formation of an electrical feature such as a conductive feature. The precursor composition advantageously has a low viscosity enabling deposition using direct-write tools. The precursor composition also has a low conversion temperature, enabling the deposition and conversion to an electrical feature on low temperature substrates. A particularly preferred precursor composition includes silver metal for the formation of highly conductive silver features.

Low viscosity precursor compositions and methods for the deposition of conductive electronic features

A solar cell that is readily manufactured using processing techniques which are less expensive than microelectronic circuit processing. In preferred embodiments, printing techniques are utilized in selectively forming masks for use in etching of silicon oxide and diffusing dopants and in forming metal contacts to diffused regions. In a preferred embodiment, p-doped regions and n-doped regions are alternately formed in a surface of the wafer through use of masking and etching techniques. Metal contacts are made to the p-regions and n-regions by first forming a seed layer stack that comprises a first layer such as aluminum that contacts silicon and functions as an infrared reflector, second layer such titanium tungsten that acts as diffusion barrier, and a third layer functions as a plating base. A thick conductive layer such as copper is then plated over the seed layer, and the seed layer between plated lines is removed. A front surface of the wafer is preferably textured by etching or mechanical abrasion with an IR reflection layer provided over the textured surface. A field layer can be provided in the textured surface with the combined effect being a very low surface recombination velocity.

Solar cell and method of manufacture

In one embodiment, harmful solar cell polarization is prevented or minimized by providing a conductive path that bleeds charge from a front side of a solar cell to the bulk of a wafer. The conductive path may include patterned holes in a dielectric passivation layer, a conductive anti-reflective coating, or layers of conductive material formed on the top or bottom surface of an anti-reflective coating, for example. Harmful solar cell polarization may also be prevented by biasing a region of a solar cell module on the front side of the solar cell.

Preventing harmful polarization of solar cells

A carrier includes a support frame (10) on which a plurality of wafers (12) are mounted with at least one auxiliary frame (20) for holding the wafers on the support frame. A plurality of clips (24) extend from the auxiliary frame and engage the wafers in pressure engagement, and fasteners (32) retain the auxiliary frame in position with the support frame. Two auxiliary frames can be employed for holding the wafers on opposing sides of the support frame. The support frame and auxiliary frame have electrically nonconducting surfaces. The clips extending from the auxiliary frame are electrically conductive and bridge current from the support frame to the wafers during plating operations. The support frame can also be made to include wafer retention clips, so that the auxiliary frame is not used. The carrier support of the invention can support multiple wafers and yield no significant mechanical stress on the wafers during processing.

Substrate carrier for electroplating solar cells

In one embodiment, backside-contact solar cells (220) in a solar cell array are connected using separate pieces of interconnect leads (202). Each interconnect lead (202) may electrically connect a contact point on a backside-contact solar cell (220) to a corresponding contact on another backside-contact solar cell (220). Each interconnect lead (202) may be curved to provide strain relief.

Solar cell interconnect structure

Solar cell interconnects with multiple current paths. A solar cell interconnect may include a plurality of in-plane slits arranged in several rows. The in-plane slits may be spaced to provide strain relief without unduly increasing the electrical path resistance through the solar cell interconnect. The in-plane slits may be staggered, for example.

Neil Kaminar

Papers

Solar cell and method of manufacture

Preventing harmful polarization of solar cells

Substrate carrier for electroplating solar cells

Solar cell interconnect structure

Solar cell interconnect with multiple current paths