The present invention is a class of circuits named asynchronous pulse logic (APL) circuit and designing methods for such circuits. APL replaces two of the four-phase handshakes in QDI circuits with pulses, thus breaking the timing dependencies that cause performance problems in QDI circuits. Since the pulse length in APL varies so little, it can be assumed constant. This assumption frees designers from needing to consider the effects of the inputs and outputs on the pulse length, which means timing properties can be verified locally. One embodiment of the present invention is a class of circuit design called the single-track-handshake-asynchronous-pulse-logic (STAPL), which serves as a new target for the compilation of CHP (Communication Hardware Process) programs. In one embodiment, a five-stage pulse generator is used to create a 10 transition count cycle circuit. Advantages of STAPL include a simplified solution to the charge-sharing problem and less loading from p-transistors.

Method and apparatus for an asynchronous pulse logic circuit

An embodiment of the present invention is a digital circuit (block 12 of FIG. 1) for interfacing between a first bus (10), which can operate synchronously or asynchronously, and a second bus (14), which can operate synchronously or asynchronously, the digital circuit comprising: compelled data decoders (40 and 50) connected to the first bus for receiving compelled data and decoding the compelled data; packet data decoders (52 and 45) connected to the first bus for receiving packet data and decoding the packet data; a digital storage device (28), preferably a FIFO comprising a plurality of write banks and a plurality of read banks or a FIFO comprising a plurality of dual-ported RAMs, having an input selectively connected to the compelled data decoders, the packet data decoders, and the second bus (via lines 44) for storing the decoded data and data from the second bus, the digital storage device additionally includes an output connected to the second bus (via lines 42) for outputting the stored decoded data to the second bus; compelled data encoders connected to the output of the digital storage device for encoding the stored data received from the second bus and outputting the encoded data to the first bus; and packet data encoders (34 and 36) connected to the output of the digital storage device for encoding the stored data received from the second bus and outputting the encoded data to the first bus. Preferably, multiple bits of data are progressively written into each write bank of the digital storage device within a clock cycle whereby the data is stored at a rate higher than the FIFO could store with a single bank. The first bus can operate synchronously or asynchronously and the second bus can also operate synchronously or asynchronously. The first and second buses can operate at different clock rates and have different data widths.

Programmable dual port data unit for interfacing between multiple buses

An enhanced services system for a telecommunications network includes operator equipment accessible by an operator, and a routing system for routing a call from a caller to the operator equipment. The caller may access e-mail creation and service and/or interpreter services. A method of sending an electronic message includes routing a call from a caller to operator equipment using a routing system, inputting information provided by the caller into the operator equipment to create an electronic message, and sending the electronic message to at least one recipient. A method pf translating a telephone conversation includes providing a routing system to connect to operator equipment a call from a caller, routing the call to the operator equipment using the routing system to enable communications between at least the caller and a bilingual operator, and translating at least a portion of the conversation between the caller and a third party.

System and method for providing communications services

A method and apparatus for providing a clock noise filter are described. The clock noise filter uses a transparent latch which has a trigger input and a data input. The data input is coupled to receive an input clock signal to be filtered. The output of the latch is the filtered clock signal. The filtered clock signal has a logic state which corresponds to the logic state of the input clock signal when the trigger input has a first predetermined logic state, and the filtered clock signal is inhibited from changing logic state when the trigger input has a second predetermined logic state. A trigger circuit is provided which has an input coupled to the output of the latch and an output coupled to the trigger input of the latch. The trigger circuit outputs the second predetermined logic state to the trigger input of the latch for a time interval in response to a change in logic state of the filtered clock signal and outputs the first predetermined logic state after the time interval has expired. The trigger circuit uses a delay stage to provide a delayed filtered clock signal to a logic gate. The logic gate receives the filtered clock signal and the delayed filtered clock signal and outputs the first and second predetermined logic states to the trigger input of the latch, depending upon the relative logic states of the filtered clock signal and the delayed filtered clock signal.

Clock noise filter for integrated circuits

The states of a distributed finite state machine composed of a plurality of devices are coordinated by a sequence of operations to effect a self-timed cycle. Each device is arranged to apply a voltage over one or more leads and measure the current on the corresponding leads. With the methodology, while engendering self-timed cycles, the number of leads interconnecting the devices is also minimized.

Coordinating the states of a distributed finite state machine

A clock mechanism in modules connected to a bus over which asynchronous operations are performed wherein clock pulses are generated that can clock the transmission or capture of data and the transitioning of acknowledge or synchronization lines. Each clock mechanism generates its clock pulses based on the receipt of signals associated with synchronization or acknowledge bus lines. The clock mechanism includes a multiplexer which provides to a resettable latch a signal associated with the condition of the selected line. The resettable latch, in conjunction with a delay element produces the clock pulses.

Niamh Darcy

Papers

Clocking system for asynchronous operations