The invention discloses a mixer bandwidth expansion method and an apparatus thereof. The method comprises the following steps that: a direct-current level output by a bias circuit is biased on a common source electrode metal oxide semiconductor (MOS) transistor and a common gate MOS transistor; the common source electrode MOS transistor and the common gate MOS transistor complete conversion of a radiofrequency signal from a voltage to a current and complete the conversion from a single-ended signal to a differential signal; the common gate MOS transistor and inductors of a source end and a grid end form a source end inductance negative feedback structure; the source end inductance negative feedback structure forms an input broadband matching network of a mixer through the inductor which cascades with the common source electrode MOS transistor and the source end of the common source electrode MOS transistor and absorbs a parasitic capacitance generated by a transconductance stage through the input broadband matching network. By using a technical scheme of the invention, a working frequency and the working bandwidth can be increased. An area occupied by a circuit can be saved and circuit power consumption can be saved too. Noises are less under the condition of not reducing conversion gains of the mixer.

Mixer bandwidth expansion method and apparatus thereof

The invention discloses a new type high speed prescale circuit which comprises two current mode logic latches (D-Latch) and two MIM (Metal Injection Molding) capacitors or two MOS (Metal Oxide Semiconductor) pipe capacitors which achieve a current shaping function. An MOS sampling tube source common mold point of each of the two D-Latches is respectively connected with an amplitude phase current shaping unit to change amplitudes and phases of sampling tube current ID under a large signal operation state and enlarge phase shift theta which needs to be compensated through a load RC (Remote Control) network and accordingly a higher self-oscillation frequency is obtained and the high speed pre-frequency dividing circuit is provided with a higher working efficiency and a wider frequency-dividing range. The new type high speed prescale circuit is capable of being widely applied to a phase-locked loop module or a related module of a frequency synthesizer in the radio frequency identification field.

New type high speed prescale circuit

The invention belongs to the technical field of clock frequency division, and in particular relates to a prescaler structure of a phase-locked loop of a CMOS ultra-wideband frequency synthesizer. The prescaler consists of a master differential analogue D latch and a slave differential analogue D latch, wherein each D latch has a pair of differential NMOS tubes serving as a logical part, a pair of cross-coupled positive feedback NMOS tubes serving as a latch part, two pairs of complementary PMOS tubes working at a positive clock phase and a negative clock phase respectively and serving as a dynamic load, and a pair of clock-controlled NMOS tubes serving as the dynamic bias of the logical part and the latch part respectively. In the invention, the working bandwidth of a circuit is expanded by optimizing methods for reducing an RC constant following a phase output node, increasing the RC constant of a latch phase output node, reducing internal signal excursion and the leakage current loss of a compensated latch phase, and the like; and the ratio of an upper frequency limit to a lower frequency limit of the circuit can reach about 100. The circuit of the invention has the advantages of low power consumption, low noise, wide band, high speed and the like at the same time.

Niansong Mei

Papers

CMOS ultra-wideband prescaler