A plurality of SMP modules and an IOP module communicate storage traffic via respective corresponding I/O controllers coupled to respective physical ports of a switch fabric by addressing cells to physical port addresses corresponding to the physical ports. One of the SMPs executes initiator software to partially manage the storage traffic and the IOP executes target software to partially manage the storage traffic. Storage controllers are coupled to the IOP, enabling communication with storage devices, such as disk drives, tape drives, and/or networks of same. Respective network identification registers are included in each of the I/O controller corresponding to the SMP executing the initiator software and the I/O controller corresponding to the IOP. Transport of the storage traffic in accordance with a particular VLAN is enabled by writing a same particular value into each of the network identification registers.

Storage traffic communication via a switch fabric in accordance with a vlan

The invention relates to an architecture that facilitates load balancing among a plurality of hosts and preserve session affinity to a given host. An incoming stream of data packets that include packet sessions is input to one or more forwarding mechanisms for forwarding to one or more hosts. The forwarders generate a routing function that takes into consideration host availability, and distributes session packets according to the routing function. A session is distributed to the same host to preserve session affinity. When host availability changes, a new routing function is generated, such that any new session is routed according to the new routing function and existing sessions are routed according to the old routing function. When the old routing function becomes irrelevant, it is phased out. An optimization utilizes a maximally backward compatible hash function to minimize the differences between the old and new routing functions.

Stateless, affinity-preserving load balancing

Storage gateway remote and local access to storage devices is provided in part via a target implementing bandwidth-controlled access to the devices. The target may be iSCSI-compatible, and may also optionally implement protection, security, and performance features. The protection and security features include any combination of VLANs, zoning, Logical Unit Number (LUN) masking, and encryption. The performance features include any combination of HW-accelerated Remote Direct Memory Access (RDMA), prioritized I/O operations, and service priority (such as strict priority and straight or weighted round-robin priorities). An initiator may be implemented in a Processor Memory Module (PMM) coupled to a switch fabric that is in turn coupled to a target implemented in a Fibre Channel Module (FCM). Storage traffic may be communicated as Small Computer System Interface (SCSI)- and SCSI over Transmission Control Protocol/Internet Protocol (iSCSI)-compatible information (data and commands) on the switch fabric via cellifying input/output interface devices.

Storage gateway target for fabric-backplane enterprise servers

Storage gateway remote and local access to storage devices is provided in part via an initiator implementing bandwidth-controlled access to the devices. The initiator may be iSCSI-compatible, and may also optionally implement protection, security, and performance features. The protection and security features include any combination of VLANs, zoning, Logical Unit Number (LUN) masking, and encryption. The performance features include any combination of HW-accelerated Remote Direct Memory Access (RDMA), prioritized I/O operations, and service priority (such as strict priority and straight or weighted round-robin priorities). An initiator may be implemented in a Processor Memory Module (PMM) coupled to a switch fabric that is in turn coupled to a target implemented in a Fibre Channel Module (FCM). Storage traffic may be communicated as Small Computer System Interface (SCSI)- and SCSI over Transmission Control Protocol/Internet Protocol (iSCSI)-compatible information (data and commands) on the switch fabric via cellifying input/output interface devices.

Storage gateway initiator for fabric-backplane enterprise servers

The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

Transaction based shared data operations in a multiprocessor environment

A bus interface unit includes a random-access transaction buffer and at least one pointer queue. The transaction buffer stores entries for both in-order transactions and combinable write transactions, and the pointer queue stores pointers to the buffer entries for in-order transactions so as to order the in-order transactions. When a received combinable write transaction has a writing address that falls within the address range of a stored combinable write transactions, the received transaction is merged with the stored transaction. Additionally, a method is provided for processing requested bus transactions. The bus interface unit determines if a requested transaction is a combinable write transaction. If not, address and data information for the requested transaction is loaded into an empty entry in a random-access buffer, and a pointer to that buffer entry is placed in a pointer queue. Alternatively, if the requested transaction is a combinable write transaction, the bus interface unit determines if the transaction's write address falls within the address range of a stored combinable write transaction. If so, the requested transaction is merged with the stored transaction. In a preferred embodiment, if the write address does not fall within the address range of any stored combinable write transaction, the data information for the requested transaction is loaded into an empty entry in the random-access buffer.

Bus interface unit having dual purpose transaction buffer

A cache subsystem in a data processing system is structured to place the L1 cache RAMs after the L2 cache RAMs in the pipeline for processing both CPU write transactions and L1 line-fill transactions. In this manner the lines loaded into the L1 cache are updated by all CPU write transactions without having to perform any explicit checks. The present invention also places the L1 tag RAM before the L1 data RAM for both CPU write transactions and L1 line-fill transactions, such that CPU write transactions may check that a line is in the L1 cache before updating it. L1 line-fill transactions can then check that the line to be transferred from the L2 cache to the L1 cache is not already in the L1 cache.

Pipelined non-blocking level two cache system with inherent transaction collision-avoidance

A multi-bit trie network search engine is implemented by a number of pipeline logic units corresponding to the number of longest-prefix strides and a set of memory blocks for holding prefix tables Each pipeline logic unit is limited to one memory access, and the termination point within the pipeline logic unit chain is variable to handle different length prefixes The memory blocks are coupled to the pipeline logic units with a meshed crossbar and form a set of virtual memory banks, where memory blocks within any given physical memory bank may be allocated to a virtual memory bank for any particular pipeline logic unit An embedded programmable processor manages route insertion and deletion in the prefix tables, together with configuration of the virtual memory banks

Apparatus and method of using fully configurable memory, multi-stage pipeline logic and an embedded processor to implement multi-bit trie algorithmic network search engine

Internet Protocol address prefixes are hashed into hash tables allocated memory blocks on demand after collisions occur for both a first hash and a single rehash. The number of memory blocks allocated to each hash table is limited, with additional prefixes handled by an overflow content addressable memory. Each hash table contains only prefixes of a particular length, with different hash tables containing prefixes of different lengths. Only a subset of possible prefix lengths are accommodated by the hash tables, with a remainder of prefixes handled by the content addressable memory or a similar alternate address lookup facility.

Apparatus and method using hashing for efficiently implementing an IP lookup solution in hardware

Sparsely distributed prefixes within a bitmapped multi-bit trie are compressed by one or more of: replacing a single entry table string terminating with a single prefix end node with a parent table entry explicitly encoding a prefix portion; replacing a table with only two end nodes or only an end node and an internal node with a single parent table entry explicitly encoding prefix portions; replacing two end nodes with a single compressed child entry at a table location normally occupied by an internal node and explicitly encoding prefix portions; and replacing a plurality of end nodes with a prefix-only entry located at the table end explicitly encoding portions of a plurality of prefixes. The compressed child entry and the prefix-only entry, if present, are read by default each time the table is searched. Run length encoding allows variable length prefix portions to be encoded.

Method for increasing average storage capacity in a bit-mapped tree-based storage engine by using remappable prefix representations and a run-length encoding scheme that defines multi-length fields to compactly store IP prefixes

Nicholas Julian Richardson

Papers

Bus interface unit having dual purpose transaction buffer

Pipelined non-blocking level two cache system with inherent transaction collision-avoidance

Apparatus and method of using fully configurable memory, multi-stage pipeline logic and an embedded processor to implement multi-bit trie algorithmic network search engine

Apparatus and method using hashing for efficiently implementing an IP lookup solution in hardware

Method for increasing average storage capacity in a bit-mapped tree-based storage engine by using remappable prefix representations and a run-length encoding scheme that defines multi-length fields to compactly store IP prefixes