Multilevel inverters are a type of power electronic circuit that converts direct current (DC) to alternating current (AC) for use in high-voltage and high-power applications. Many recent studies on multilevel inverters have used field-programmable gate arrays (FPGAs) as a switching controller device to overcome the limitations of microcontrollers or DSPs, such as limited sampling rate, low execution speed, and a limited number of IO pins. However, the design techniques of most existing FPGA-based switching controllers require large amounts of memory (RAM) for storage of sampled data points as well as complex controller architectures to generate the output gating pulses. Therefore, in this paper, we propose two types of FPGA-based digital switching controllers, namely selective harmonic elimination (SHE) and sinusoidal pulse width modulation (SPWM), for a 21-level multilevel inverter. Both switching controllers were designed with minimal hardware complexity and logic utilisation. The designed SHE switching controller mainly consists of a four-bit finite state machine (FSM) and a 13-bit counter, while the SPWM switching controller employs a simple iterative CORDIC algorithm with a small amount of data storage requirement, a six-bit up-down counter, and a few adders. Initially, both digital switching controllers (SHE and SPWM) were designed using the hardware description language (HDL) in Verilog codes and functionally verified using the developed testbenches. The designed digital switching controllers were then synthesised and downloaded to the Intel FPGA (DE2-115) board for real-time verification purposes. For system-level verification, both switching controllers were tested on five cascaded H-Bridge circuits for a 21-level multilevel inverter model using the HDL co-simulation method in MATLAB Simulink. From the synthesised logic gates, it was found that the designed SHE and SPWM switching controllers require only 186 and 369 logic elements (LEs), respectively, which is less than 1% of the total LEs in an FPGA (Cyclone IV E) chip. The execution speed of the SHE switching controller implemented in the FPGA (Cyclone IV E) chip was found to be a maximum of 99.97% faster when compared with the microcontroller (PIC16F877A). The THD percentage of the 21-level SHE digital switching controller (3.91%) was found to be 37% less than that of the SPWM digital switching controller (6.17%). In conclusion, the proposed simplified design architectures of SHE and SPWM digital switching controllers have been proven to not only require minimal logic resources, achieve high processing speeds, and function correctly when tested on a real-time FPGA board, but also generate the desired 21-level stepped sine-wave output voltage (±360 VPP) at a frequency of 50 Hz with low THD percentages when tested on a 21-level cascaded H-Bridge multilevel inverter model.

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Design of FPGA-Based SHE and SPWM Digital Switching Controllers for 21-Level Cascaded H-Bridge Multilevel Inverter Model

According to the increase of Multi-Level Inverter (MLI) applications in distributed generations, a novel single-phase grid-connected MLI topology is proposed in this paper. The proposed inverter is planned to feed the utility grid from renewable energy sources (RESs) to overcome the issue of output sinusoidal waveform in conventional MLIs by generating a multilevel waveform with too many levels, and fewer switches count. The proposed structure is fault-tolerant and modular. A detailed analysis of the proposed topology for two different 13 and 20 switches have been carried out to show its superiority over the conventional MLI topologies. The 79-level and 321-level of the proposed MLI are designed and simulated in MATLAB/SIMULINK environment. After a precise simulation, due to compliance with the IEC 61727–2004, about total harmonic distortion (THD) of output voltage and current, there is no need to use extra output filter.

A New Reduced Switch Multilevel Inverter for PV Applications

Lately, a multilevel inverter takes an emergent role for medium voltage and high-power applications. It has many advantages like low switching loss, high dv/dt stress, low THD. But it has also disadvantage like for higher level required more switching devices, huge size, high cost. This paper mainly proposed a newly invented topology with a reduced switch belongs to only eight switches, four voltage sources, and two power diodes to produce twenty-one level voltage waveforms. The major advantage of this proposed inverter ends in diminished size, lesser loss, along with low installation cost, and it is suitable for high power applications. The simulation results for different switching angle calculation methods especially Equal Phase (EP) method and Half Height (HH) method are analyzed and presented. The proposed inverter has been simulated through MATLAB software.

A New Single Phase 21 Level Inverter Topology with Reduced Number of Switches and Sources for Renewable Energy Applications

Multilevel inverters (MLIs) are extremely influential in renewable energy systems, are used to convert DC power into AC. MLIs are more beneficial in comparison to the two-level conventional inverter in terms of lower total harmonic distortion (THD), lesser electromagnetic interference (EMI), increases the capability of fault tolerance, and are more efficient. The major aspect of this review article is to analyze the recent (MLI) topologies into two categories which are symmetric and asymmetric configuration which contains the reduced number of switches $(\mathrm{N}_{\mathrm{S}\mathrm{W}})$. currently, Researchers have an eye on the using reduced number of components in MLI topologies for lesser voltage stress and high efficiency. Performance parameters such as total standing voltage (TSV), THD, and modulation techniques are briefly discussed in this article. furthermore, the general comparison of these topologies is depicted in tabular & graphical representation based on the required number of switches, number of the gate drivers $(\mathrm{N}_{\mathrm{G}\mathrm{D}})$, Number of dc voltage sources $(\mathrm{N}_{\mathrm{D}\mathrm{C}})$, THD, and the number of level $(\mathrm{N}_{\mathrm{L}})$ that are obtained through the multilevel inverter topologies.

Symmetrical and Asymmetrical Multilevel Inverter Topologies With Reduced Device Count: A Review

In this paper, a 21 level multi-sourced inverter with reduced switch, and component count is proposed. The proposed multilevel inverter (MLI) is asymmetrically switched to achieve maximum level from the planned cascaded topology. Multicarrier Pulse Width Modulation technique (MCPWM) is used as a control technique for the proposed inverter. As the inverter is asymmetrically switched, the switch logic for the proposed inverter is generated using Boolean expressions through logical implementation. The power quality, i.e., THD of the proposed inverter, is shown for different types of MCPWM methods such as PD, POD, and APOD for the resistive and inductive load as well. The proposed inverter has also been implemented through HIL (hardware in the loop) using the FPGA-based OPAL-RT module. As separate DC sources need to be used as input for the suggested topology, it can be utilized for renewable power generation, especially Grid-Connected PV System (GCPV).

MCPWM Based 21 Level Inverter Design for Grid Connected PV System

This paper presents an asymmetrical multilevel inverter topology with Different PWM techniques. This paper used one cell of conventional cascade H-Bridge Multilevel inverter structure with additional switch and voltage source to obtain high voltage level. The aim of this paper to enhance the voltage level at the output with using less switch. To improve the output voltage harmonic spectrum, the pulse width modulation (PWM) techniques used. The advantage of this proposed topology to reduce the circuit complexity and total harmonic distortion. The results of proposed 21-Level Asymmetrical multilevel Inverter are shown using MATLAB/SIMULINK software.

A new 21-level asymmetrical multilevel inverter topology with different PWM techniques

Multilevel inverters are the versatile tool for running highly rated machines. However it can work satisfactorily for medium and low rating machines, concerning to their advantages like lower EMI, suppressed harmonic distortion and higher DC-link voltages it is manifolds better to a conventional two level inverter. Their main drawback is complexity, Because it requires large number of batteries and switches. In this paper a symmetrical inverter topology for generation of nine levels of output voltage with reduced number of switches is presented. This technology employs lesser circuit elements compared to other techniques hence significantly reduces the complexity. The performance of present technology is executed by MATLAB/SIMULINK platform and the results showing the operation of the present topology as multilevel inverter is presented.

Various modulation techniques in symmetrical multilevel inverters

This paper presents a new single phase H-bridge multilevel inverter topology using reverse- connected voltage source along with a different pulse width modulation (PWM) strategy, to extract a variable frequency variable amplitude output voltage. It involves the use of reduced number of switching devices for a specific number of output voltage levels in comparison with conventional MLIs. Using this configuration, the total harmonic distortion is reduced as total harmonic distortion plays an important role in medium voltage and high power applications for better operation so here with new proposed topology the total harmonic distortion diminishes. In this paper simulation results of the proposed multilevel inverter for a single-phase 7- level multilevel inverter are presented and the total harmonic distortions results of 7, 9, 11-level with different modulation index are shown.

A multilevel inverter topology using reverse-connected voltage sources

This paper studies a new reduced component multilevel inverter topology using different modulation techniques to obtain the desired output. The great innovation has been done in the past two decades and their improved performance is challenging even today, many researchers work on to improve their performance and make it cost-effective. The proposed topology used low number of components compare to conventional multilevel inverter and used the PWM techniques to improve their performance, i.e., total harmonic distortion (THD) as inverter performance measures in two factors: one is distortion factor and second one is total harmonic distortion(THD). This paper simulated the result for 7 level to 15 levels with different modulation indices and modulation techniques.

Nikhil Agrawal

Papers

A new 21-level asymmetrical multilevel inverter topology with different PWM techniques

Various modulation techniques in symmetrical multilevel inverters

A multilevel inverter topology using reverse-connected voltage sources

THD Analysis of New Multilevel Inverter Topology with Different Modulation Techniques