A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells The changing step includes determining a history read reference level for correct reading of at least one history cell, selecting a memory read reference level according to the first read reference level, and reading non-volatile memory array cells associated with the at least one history cell using the memory read reference level

Method for reading non-volatile memory cells

In a non-volatile memory, the read parameter used to distinguish the data states characterized by a negative threshold voltage from the data states characterized by a positive threshold voltage is compensated for the memory's operating conditions, rather than being hardwired to ground. In an exemplary embodiment, the read parameter for the data state with the lowest threshold value above ground is temperature compensated to reflect the shifts of the storage element populations on either side of the read parameter. According to another aspect, an erase process is presented that can take advantage the operating condition compensated sensing parameter. As the sensing parameter is no longer fixed at a value corresponding to 0 volts, instead shifting according to operating conditions, a sufficient margin is provided for the various erase verify levels even at lowered operating voltages.

Read and erase verify methods and circuits suitable for low voltage non-volatile memories

A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.

Multiple use memory chip

Coarse/fine programming of non-volatile memory is provided in which memory cells are programmed at a first rate of programming prior to reaching a coarse verify level for their intended state and a second rate of programming after reaching the coarse verify level but before reaching the final verify level for their intended state. Large sub-threshold swing factors associated with smaller memory cells can affect the accuracy of sense operations, particularly when sensing at a fine verify level after sensing at a coarse verify level without pre-charging the bit line between the different sensings. Different reference potentials are utilized when sensing at a coarse verify level and a final verify level. The different between the reference potentials can compensate for any discharge of the bit line during the coarse level sensing.

Coarse/fine program verification in non-volatile memory using different reference levels for improved sensing

A charge pump stage includes a first n-channel transistor having a source coupled to an input terminal and a drain coupled to an output terminal. A second n-channel transistor has a source coupled to the input terminal, a drain coupled to a gate of the first transistor, and a gate coupled to the output terminal. A third n-channel transistor has a source coupled to the input terminal, a gate coupled to the output terminal, and a drain coupled to a p-well. A fourth n-channel transistor has a source coupled to the output terminal, a gate coupled to the input terminal, and a drain coupled to the p-well. The first, second, third and fourth transistors are fabricated in the p-well, which is surrounded by an n-well. A first capacitor is coupled to the output terminal, and a second capacitor is coupled to the gate of the first transistor.

Triple-well charge pump stage with no threshold voltage back-bias effect

Non-volatile memory (NVM) cells are sensed using a forced neighbor signal to eliminate improper readings generated by a neighbor effect. A selected NVM cell is sensed using a near-ground signal by applying a potential to a first terminal, coupling a second terminal to ground, and then decoupling the second terminal and comparing the resulting cell signal with a reference signal as both signals are developing (i.e., increasing from ground). A forced neighbor signal is applied to one more neighboring cells such that as the sensed cell signal develops (increases from ground), the forced neighbor signal develops at a similar rate, thereby maintaining a voltage across the neighboring cells close to zero and thus preventing leakage of the sensed cell signal through the neighbor cell(s). A dc sensing approach utilizes a current source and grounded resistor to minimize leakage through the neighbor cell(s).

Neighbor effect cancellation in memory array architecture

A non-volatile memory (NVM) system including an array of NVM cells, a column decoder, a set of comparators and a corresponding set of NVM reference blocks is provided During a read operation, the column decoder routes a set of read output voltages from an addressed set of the NVM cells Each of the read output voltages is applied to a first input terminal of a corresponding comparator Each NVM reference block generates a distinct reference voltage that is applied to a second input terminal of a corresponding comparator Each NVM reference block is programmed to generate its distinct reference voltage in response to a random internal offset voltage in the corresponding comparator Compensating the reference voltages in this manner enables all comparators to provide consistent results during a read operation

Sense amplifier offset cancellation in non-volatile memory circuits by dedicated programmed reference non-volatile memory cells

Low voltage sensing circuits for non-volatile memory (NVM) devices including a comparator (operational amplifier) having input terminals connected to the gate terminals of first and second PMOS transistors. The PMOS transistors are coupled between a system voltage source and respective bit lines carrying cell and reference currents from a selected NVM cell and a reference NVM cell, respectively. To facilitate low system voltages, voltage supply or source-follower circuits are connected between the gate and drain terminals of each PMOS transistor such that the bit line voltages are increased without increasing the voltage signals applied to the input terminals of the comparator, and without the use of charge pumps.

Low voltage sensing circuit for non-volatile memory device

Operation of conventional nitride read-only-memory (NROM) cells is modified, such that each charge trapping region of an NROM cell is capable of storing any one of three charge states. For example, each charge trapping region can have an erased state, a first programmed state, or a second programmed state. Each of these states results in a different threshold voltage. During a read operation, the threshold voltages associated with two charge trapping regions are identified and decoded to provide a 3-bit data value. If each NROM cell includes two separate charge trapping regions, two NROM cells can store a total of 6-bits of data. The average storage density is therefore increased from two bits per NROM cell to three bits per NROM cell.

Noam Eshel

Papers

Triple-well charge pump stage with no threshold voltage back-bias effect

Neighbor effect cancellation in memory array architecture

Sense amplifier offset cancellation in non-volatile memory circuits by dedicated programmed reference non-volatile memory cells

Low voltage sensing circuit for non-volatile memory device

3-Bit NROM flash and method of operating same