A novel super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

A super-self-aligned trench-gate dmos with reduced on-resistance

To provide a highly reliable semiconductor device which does not suffer from a crack in its package, a semiconductor chip 12 is mounted on a lead frame 11 with a bonding layer 13 between them, and they are sealed with a sealing resin 14. The lead frame 11 has a base member 11a essentially consisting of Cu and an oxide film 11b essentially consisting of an oxide of the base member 11a formed on the base member and having a thickness of about 50 nm or below. By controlling the oxide film 11b to a thickness of about 50 nm or below, an adhesion strength with the sealing resin 14 is improved greatly, so that a package crack does not occur even if a large thermal load is applied in a reflow process for mounting.

Semiconductor device, and manufacturing method of the same

A semiconductor device, which can have a uniform film on open ends of trenches by using materials having a different oxidation rate, and a fabrication method thereof are provided. The semiconductor device having trenches configured to have open ends covered with an oxidation film made of a material having an oxidation rate faster than that of a semiconductor substrate and a fabrication method thereof are provided.

Semiconductor gate trench with covered open ends

A novel super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid-process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

Super-self-aligned fabrication process of trench-gate DMOS with overlying device layer

A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

Fabrication process for a super-self-aligned trench-gated DMOS with reduced on-resistance

PURPOSE:To obtain a P-type substrate semiconductor device which has a high withstand voltage and has no change in the withstand voltage with the passage of time by forming a hole trap level, in an oxide film on the surface of the substrate by casting electron beams. CONSTITUTION:By forming a hole trap level 16 in an oxide film 6 on the surface of a P-type semiconductor substrate 1 by casting electron beams, an N-type reverse layer 15 is formed on the surface of the P-type semiconductor substrate 1. This N-type inversion layer 15 expands a depletion layer 17 which is formed at the collector side of a PN junction when a reverse bias is applied, into a deep region of an element diffusion region, alleviates a curvature of the depletion layer 17, and increases the breakdown voltage. When movable ions in the oxide film 6 are drawn near to the boundary of the semiconductor substrate 1 in a high-temperature reverse bias test(BT), the N-type reverse layer 15 gets only a little bit deeper and there is little influence on the distribution of the ions in the depletion layer 17. Therefore, there is no change in the breakdown voltage.

Semiconductor device and manufacture thereof

PROBLEM TO BE SOLVED: To avoid the effect of dispersion at the time of the formation of a LOCOS oxide film on the impurity concentration of a diffusing region for high-voltage resistance by setting the concentration peak of the one-conducting type diffusing region for high-voltage resistance at the position deeper than the deepest interface region of the LOCOS oxide film and a drain region. SOLUTION: The concentration peak CP of a one-conducting type diffusing region 3 for high-voltage resistance is set at a position deeper than the deepest interface region between a LOCOS oxide film 5 and a drain region 8. Most of the regional area shown in a shaded part is present in the region deeper than the interface region of the LOCOS oxide film 5. Even when there is dispersion in film thickness (arrow mark), the total amount of impurities in the diffusing region 3 for high-voltage resistance becomes more than the conventional amount. Therefore, even if there is dispersion in the LOCOS oxide film 5 in the depth direction, the impurity concentration of the diffusing region itself for high-voltage resistance has no dispersion in comparison with the conventional device. Therefore, the voltage resistance characteristic of the horizontal high- voltage resistance MOSFET can be made uniform.

Noguchi Yasunari

Papers

Semiconductor device and manufacture thereof

Semiconductor device and manufacture of semiconductor device