Quasi-two-dimensional (2-D) device analyses, 2-D numerical device simulations, and circuit simulations of nanoscale conventional, single-gate fully depleted (FD) silicon-on-insulator (SOI) CMOS are done to examine the scalability and performance potential of the technology. The quasi-2-D analyses, which can apply to double-gate devices as well, also provide a simple expression to estimate the effective channel length (L/sub eff/) of FD/SOI MOSFETs. The insightful results show that threshold-voltage control via channel doping and polysilicon gates is not a viable option for extremely scaled FD/SOI CMOS, and hence that undoped channels and metal gate(s) with tuned work function(s) must be employed. Quantitative as well as qualitative insights gained on the short-channel effects reveal the need for ultrathin films (t/sub Si/ < 10 nm) for L/sub eff/ < 50 nm. However, the implied manufacturing burden, compounded by effects of carrier-energy quantization for ultrathin t/sub Si/, forces a pragmatic limit on t/sub Si/ of about 5 nm, which in turn limits the scalability to L/sub eff/ = 25-30 nm. Unloaded CMOS-inverter ring-oscillator simulations, done with our process/physics-based compact model (UFDG) in SPICE3, show very good performance for L/sub eff/ = 35 nm, and suggest viable technology designs for low-power as well as high-performance applications. These simulations also reveal that moderate variations in t/sub Si/ can be tolerated, and that the energy quantization significantly influences the scaled-technology performance and hence must be properly accounted for in optimal FD/SOI MOSFET design.

Scaling fully depleted SOI CMOS

The threshold voltage shifts (/spl Delta/V/sub t(SS)/ relative to V/sub t/ of Si-control devices) in strained-Si-Si/sub 1-x/Ge/sub x/ (SS) CMOS devices are carefully examined in terms of the shifted two-dimensional energy subbands and the modified effective conduction- and valance-band densities of states. Increased electron affinity as well as bandgap narrowing in the SS layer are shown to be the predominant components of /spl Delta/V/sub t(SS)/, whereas the density-of-state terms tend to be relatively small but not insignificant. The study reveals, for both n-channel and p-channel SS MOSFETs, important physical insights on the varied surface potential at threshold, defined by energy quantization as well as the strain, and on the shifted flat-band voltage that is also part of /spl Delta/V/sub t(SS)/. Models for /spl Delta/V/sub t(SS)/ dependent on the Ge content (x), with comparisons to published data, are presented and used to show that redesign of channel doping in the SS nMOSFET to increase the significantly reduced V/sub tn(SS)/ for off-state current control tends to substantively diminish the inherent SS CMOS relative speed enhancement, e.g., by more than 40% for x=0.20. Interestingly, the SS pMOSFET model predicts small increases in the magnitude of V/sub tp(SS)/.

On the threshold Voltage of strained-Si-Si/sub 1-x/Ge/sub x/ MOSFETs

A novel partial-ground-plane (PGP)-based MOSFET on a selective buried oxide (SELBOX), named PGP-SELBOX, is proposed. An extensive simulation study and the comparative analysis of the key characteristics of the PGP-SELBOX, the SELBOX, and the conventional silicon-on-insulator (SOI) devices has been performed using the 2-D device simulator Medici. The simulations have revealed that the PGP-SELBOX and the SELBOX structures are more thermally efficient than the conventional SOI device. Further, the magnitude of the short-channel effects (SCEs) is lower in the PGP-SELBOX in comparison to the SELBOX device. Though the SCE suppression is best in the thin-film SOI device, the PGP-SELBOX shows better improvement in SCE suppression in comparison to the SELBOX device. The suppression of self-heating effects and SCEs in the PGP-SELBOX results in a significant reduction in leakage current. An improved performance in terms of I ON/I OFF ratio is obtained in the PGP-SELBOX device. Further, the fT values of the PGP-SELBOX are comparable to those of the SELBOX and the SOI devices. A process flow in which a low-dose separation by implantation of oxygen technique can be employed for the fabrication of the PGP-SELBOX is also proposed.

A Novel Partial-Ground-Plane-Based MOSFET on Selective Buried Oxide: 2-D Simulation Study

The question of buried-oxide (BOX) thickness scaling for nanoscale fully depleted (FD) silicon-on-insulator (SOI) CMOS is addressed via insightful quantitative and qualitative analyses. Whereas, FD/SOI MOSFETs with thin BOX give better control of short-channel effects (SCEs), they complicate the material and/or process technologies and undermine CMOS speed. We show that the improved SCE control afforded by thin BOX is due to high transverse electric field in the body defined by the device asymmetry, and not only to the suppression of electric-field fringing in the BOX as is commonly presumed. Since conventional FD/SOI CMOS with thick BOX can be scaled via ultrathin bodies, we conclude that thin BOX is not needed nor desirable.

Nanoscale FD/SOI CMOS: thick or thin BOX?

This paper presents a quantitative study on the device design for the control of threshold-voltage and the suppression of short-channel effects (SCEs) in ultrathin strained-silicon-on-insulator (strained-SOI) CMOSFETs in the sub-100-nm regime. A two-dimensional device simulation is used for this purpose, with emphasis on the impact of band offset in Si/SiGe heterostructures. For the control of threshold-voltage, the combination of the gate work function and the back gate bias is needed to obtain appropriate values of threshold-voltage in n- and p-channel MOSFETs and to suppress SiGe buried channels in p-channel MOSFETs with thicker strained-Si layers. Regarding SCEs, the importance and the necessity of thin SiGe layers are pointed out from the viewpoint of the influence of the higher permittivity of SiGe layers. It is shown that the SCEs of strained-SOI MOSFETs with thinner SiGe layers are almost the same level as those of unstrained-SOI.

Control of threshold-voltage and short-channel effects in ultrathin strained-SOI CMOS devices

Device design issues regarding threshold voltage (V/sub th/) control, short channel effects (SCE) and subthreshold slope are quantitatively studied for fully-depleted (FD) SOI MOSFETs under the sub-100 nm regime. As for the Vth adjustment method, the combination of back gate bias (V/sub g2/) and gate work function (/spl Phi//sub m/) control is found to provide superior SCE, V/sub th/ fluctuation due to SOI thickness variation and current drive. As for the subthreshold slope (SS), on the other hand, the optimization of thickness and permittivity of buried oxides is a key issue. It is found that, when the gate length is less than 100 nm, SS has a minimum value at buried oxide thickness of around 40 nm, irrespective of SOI thickness. It is also shown that the reduction in the permittivity of buried oxides improves SS.

Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs

In this paper threshold voltage, subthreshold slope and short channel effects, in strained-SOI n-MOSFET and p-MOSFET are examined quantitatively, with emphasis on the impact of band offset in Si/SiGe heterostructure, by two dimensional device simulation.

Numata

Papers

Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs

Control of threshold voltage and short channel effects in ultra-thin strained-SOI CMOS