The inability to accurately determine the die level current draw of microprocessors is a significant gap in the analysis and design of microprocessor power delivery networks (PDNs). Although low frequency methods of direct measurement are available, the large number of power and ground connections on a package makes high frequency measurements extremely difficult. This paper successfully demonstrates that the instantaneous load current can be accurately estimated to over 500 MHz with only a wide bandwidth measurement of the voltage at the die. The current estimate is obtained by using the measured output impedance to create a band-limited inverse filter to solve the linear deconvolution problem. The accuracy of the algorithm is verified by correctly estimating known loads drawn by a functioning microprocessor. Two separate methods are then used to estimate the instantaneous load current of a microprocessor executing instructions, and wide bandwidth io (t) results are presented and discussed.

Estimation of Microprocessor Instantaneous Load Current

A concise method for estimating the instantaneous current drawn by a microprocessor as a function of time is presented. The approach uses the measured output impedance to create an extrapolated, band-limited inverse filter which estimates the instantaneous load current from a highly averaged measurement of the output voltage. The algorithm is verified in simulation and measured results are presented.

Estimation of microprocessor instantaneous load current for voltage regulator optimization

In this paper, we present a new embedded current probe that can support measurement-based approach for extracting switching current waveform that was injected into power distribution network (PDN). The proposed embedded current probing structure utilizes magnetic coupling behavior between primary conducting via and secondary toroidal coil structure surrounding and it can be used as a sensor which relates the induced voltage across toroidal coil to the switching current of conducting via. This paper will present characterization of magnetic coupling behavior of proposed embedded current probing structure, demonstration of proposed current extraction method by implementing the current probing structure in a board level PDN and validation of SSN analysis by applying the extracted current waveform through the simulation and measurement result.

Design and implementation of magnetically coupled current probe for monitoring simultaneous switching current in package

The IC (integrated circuit) packaging technology has evolved and transitioned from wirebond to flipchip, multi-chip package (MCP) to 3D stacking. PoP (Package on Package) enables the vertical integration of memory on the conventional package which helps to achieve higher component density on the platform. PoP technology is very important for modern electronics devices as it features more function in very compact devices such as smart phones and tablets. While PoP offers denser component count on platform, it also comes with electrical challenges such as Power Integrity issue. Conventional Power Integrity Design and Methodology may not hold for PoP technology.

Package on package DDR Power Integrity Design

Traditionally, power integrity engineer uses simulated transient current profile, icc(t) from the Circuit Designer as input to power delivery network, PDN to simulate worst case transient power noise. However, it is extremely difficult to simulate the maximum current profile from large circuit or logic block. It increases the difficulties when the circuit/ logic run at random application. The paper discusses the reverse engineering method to regenerate high speed stimulus current from the given PDN and measured voltage waveform. The paper firstly verified that the reverse engineering method proven to be accurate in HSPICE simulation. Then measurement technique is applied to an Intelreg Core 2 Duo Processor running stress test under various random applications. The paper also discusses the precision and reproducibility of high speed current profile, icc(t) by using this reverse engineering technique. The finding enables the transient power simulation of a PDN can be done without depending on the simulated CKT/ Logic block icc(t) data. The method also improves the correlation work to be done between the pre-silicon simulated icc(t) with the measurement data from the lab.

O.A.Y. Yeong

Papers

Study of High Speed Current Excitation Reverse Engineering Methodology Using Measured Voltage and PDN Impedance Profile from a Running Microprocessor