This study presents new low-power multiple-valued logic (MVL) circuits for nanoelectronics. These carbon nanotube field effect transistor (FET) (CNTFET)-based MVL circuits are designed based on the unique characteristics of the CNTFET device such as the capability of setting the desired threshold voltages by adopting correct diameters for the nanotubes as well as the same carrier mobility for the P- and N-type devices. These characteristics make CNTFETs very suitable for designing high-performance multiple- V th circuits. The proposed MVL circuits are designed based on the conventional CMOS architecture and by utilising inherently binary gates. Moreover, each of the proposed CNTFET-based ternary circuits includes all the possible types of ternary logic, that is, negative, positive and standard, in one structure. The method proposed in this study is a universal technique for designing MVL logic circuits with any arbitrary number of logic levels, without static power dissipation. The results of the simulations, conducted using Synopsys HSPICE with 32 nm-CNTFET technology, demonstrate improvements in terms of power consumption, energy efficiency, robustness and specifically static power dissipation with respect to the other state-of-the-art ternary and quaternary circuits.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2013.0023

A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits

Data processing optimization is one of the main concerns for developing of multiple-valued logic. An advantage could be achieved by realization of new functions existing in non-binary logic. These new logic functions could be implemented using quaternary look-up tables. In this work, a quaternary multiplexer circuit is designed to implement any n-variable quaternary logic function based on its truth table. Voltage-mode CMOS with multi-threshold transistors and multi-Vdd quaternary design was suggested. The multiplexer circuit consists of quaternary down literal circuits, binary inverters and binary pass transistor gates. All circuits were simulated with the Spice tool using TSMC 0.18 mum technology and have shown improvements in performance and power consumption and using less transistors than their equivalent binary circuits.

Quaternary Look-Up Tables Using Voltage-Mode CMOS Logic Design

In this paper we discuss timing details and performance of the ultra low voltage (ULV) logic style. The ULV logic gates can be utilized to design high speed systems operating at ultra low supply voltages. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offsets voltages are used to shift the effective threshold voltage of the evaluating transistors. The simulated data presented is obtained using the Spectre simulator provided by Cadence and valid for a 90 nm CMOS process.

High Speed Ultra Low Voltage CMOS inverter

In this paper we present a CMOS gate which operates on ultra low voltage. We show how to reduce the supply voltage Vdd to Vt without affecting the operational frequency significantly. Moreover, we elaborate on the PDP and EDP improvement compared to footed domino logic CMOS. The paper concludes with measurement from a fabricated chip in a 0.13mum process.

Ultra low voltage CMOS gates

In this paper, the authors present pseudo-floating-gate (PFG) binary and analog inverters with feedback control The PFG inverter can be used to implement digital, multiple-valued (MV) and analog circuits The PFG inverter will suppress low frequency components due to a local feedback PFG circuits can be utilized for low voltage (LV) binary-, multiple valued logic and analog circuits Typical applications are detection of high frequency components in sensory signals, ie airbag sensors A differential LV amplifier is presented Simulated data is valid for a CMOS process with at threshold voltage equal to 04V The circuits has been implemented in a 130nm CMOS process

Pseudo Floating-Gate Inverter with Feedback Control

In this paper we present novel recharged logic for multiple-valued (MV) systems by utilizing semi-floating-gate (SFG) transistors. The recharged multiple-valued logic can be used to implement low-power digital circuits. The improvement in power dissipation is mainly in reduced dynamic power dissipation. The main purpose is to level out the power dissipated by a digital system to obtain more suitable logic for mixed mode design.

O. Minnotahari

Papers

Novel recharge semi-floating-gate CMOS logic for multiple-valued systems