A light emitting element includes a multi-layered structure including an n-type nitride compound semiconductor layer and a p-type nitride compound semiconductor layer stacked on a substrate, and the multi-layered structure has formed an n-type region extending through the p-type semiconductor layer down to the n-type semiconductor layer to permit the p-side electrode and the n-side electrode to be formed on a common plane. A high-resistance region may be formed to surround the n-type region in order to more effectively block a leak current produced between the n-type region and the p-type nitride compound semiconductor. The light emitting element therefore includes no step on its surface, which simplifies the wafer process and contributes to wider applications of the semiconductor light emitting elements.

Semiconductor light emitting element, its manufacturing method and light emitting device

A wafer having heterostructure therein is formed using a substrate with recesses formed within a dielectric layer. A magnetized magnetic layer or a polarized electret material is formed at the bottom of each recess. The magnetized magnetic layer or a polarized electret material provides a predetermined magnetic or electrical field pattern. A plurality of heterostructures is formed from on an epitaxial wafer wherein each heterostructure has formed thereon a non-magnetized magnetic layer that is attracted to the magnetized magnetic layer formed at the bottom of each recess or dielectric layer that is attracted to the polarized electret material formed at the bottom of each recess. The plurality of heterostructures is etched from the epitaxial wafer to form a plurality of heterostructure pills. The plurality of heterostructure pills is slurried over the surface of the dielectric layer so that individual heterostructure pills can fall into a recess and be retained therein due to the strong short-range magnetic or electrical attractive force between the magnetized magnetic layer in the recess and the non-magnetized magnetic layer on the heterostructure pill or between the polarized electret material in the recess and the dielectric on the heterostructure pill. Any excess heterostructure pills that are not retained in a recess formed within the dielectric layer are removed and an overcoat is applied to form a substantial planar surface.

Method and system for magnetically assisted statistical assembly of wafers

A bipolar transistor is provided with an external base region. The bipolar transistor comprises a first semiconductor layer of a first conductivity type, the first semiconductor layer serving as a collector region, a second semiconductor layer of a second conductivity type, which is formed on the first semiconductor layer and includes a base region and an external base region located around the base region, a third semiconductor layer of the first conductivity type, which is formed on the second semiconductor layer and serves as an emitter region, a metal layer formed on the third semiconductor layer and serving as an emitter electrode, the metal layer including a first metal layer portion which is substantially as wide as the base region located in an intrinsic transistor region, and a second metal layer portion which is formed on the first metal layer portion and is wider than the first metal portion, a base electrode located on the external base region of the second semiconductor layer, and a collector electrode connected to the first semiconductor layer.

Bipolar transistor having external base region

An AlGaAs/GaAs heterojunction bipolar transistor in which a base doping concentration is set to be as very high as 5×1019 cm-3 or more to cause a band gap narrowing effect and to reduce a band gap difference by an amount corresponding to the band gap narrowing effect, an Al composition ratio, ie, x in an Alx Ga1-x As material of an emitter layer is set to be less than 025, whereby an emitter resistance can be made small, an operating speed can be made fast and a current gain can be made high Preferably, the base doping concentration is set to be 12×1020 cm-3 or more so that the operation speed can be made remarkably fast

Heterojunction bipolar transistor

A semiconductor device comprises a substrate (31-33), at least one field effect transistor (Q3, Q4, Q11, Q12, Q13, Q22) provided on the substrate, and at least one level shift diode (D1-D4) provided on the substrate, where the level shift diode comprises a first layer (12, 34B, 54b, 62a, 62c, 74b, 82a, 82c) made of a first compound semiconductor and a second layer (13, 34C, 61a, 61c, 63a, 63c, 81a, 81c, 83a, 83c) made of a second compound semiconductor having an electron affinity smaller than that of the first compound semiconductor. The first and second layers form a heterojunction therebetween. The first and second compound semiconductors are both made of either one of n-type and i-type (or either one of p-type and i-type) semiconductors, and the first layer is used in common with the field effect transistor as a layer of the field effect transistor.

Semiconductor device having level shift diode

A heterojunction bipolar integrated circuit is disclosed which uses a heterojunction bipolar transistor with a heterojunction between an emitter region (28) and a base region (30). In this transistor, a pn junction between the base region (30, 38) and the emitter region (28) has a greater area than a pn junction between the base region (30, 38) and a collector region (36). A plurality of such heterojunction bipolar transistors are isolated on a substrate to perform logic operations in an unsaturated region.

O Pat. Div. K.K. Toshiba Agaki

Papers

Heterojunction bipolar integrated circuit