The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16 , 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Integrated circuit I/O using a high performance bus interface

A system and method for accessing, controlling and monitoring a data processing device in which a video raster signal from the data processing device is analyzed to determine the information displayed on a video display monitor attached to the data processing device is used. The video raster signal is converted to a digital form and a cyclic redundancy check is performed on the digital data to determine the information contained in the video raster signal and to generate a compressed representation of that information. The information may then easily and quickly be transmitted to a remote location for analysis and review. Additionally, commands from the remote location can be transmitted to the system to control the data processing device.

System and method for remote monitoring and operation of personal computers

A remote access device is disclosed for capturing, digitizing and communicating video signals from a host computer to a remote computer. The remote computer returns keyboard and mouse signals through the remote access device to the host computer to control the host computer as though the remote keyboard and mouse were directly connected to the host computer. The remote access device includes a circuit module interface for the host computer that allows the remote access device to operate independently of any operating system characteristics associated with the host computer.

System and method for accessing and operating personal computers remotely

A selective call receiver (106) receives one or more message packets of a transmitted fragmented message, where each of the one or more message packets includes an address (1605) and message data (1610), and the message data (1610) includes an indication (1702) of whether more message packets are to be received for the fragmented message. The selective call receiver (106) receives an address of each message packet, and then correlates (2908) the address to one or more predetermined addresses. After a successful correlation (2908), the selective call receiver (106) decodes the message data (1610) of each message packet, and then successively stores (2928, 2936, 2942) the decoded message data (1610) to reconstruct the fragmented message. The selective call receiver (106) determines that the fragmented message is completely reconstructed after detection (2918) in the decoded message data (1610) an indication (1702) that no more message packets are to be received for the fragmented message.

Paging system using message fragmentation to redistribute traffic

A messaging system for selectively performing an action on information, for remote retrieval of messages, for performing action on information at different times, for selective paging, for providing a user interface for message access and having integrated audio visual messaging.

Wireless messaging method

A paging receiver device and method are disclosed in which analog information transmitted from an external source such as a paging transmitter are received and decoded. The analog information includes at least one voice message. The voice message is recovered, digitized, and stored in one of a plurality of message slots in a memory of the paging receiver. In response to a paging user's request, the digitized stored message is recalled from memory, reconverted from digital information to analog information, and used to produce audible voice information being a replica of the original analog voice message.

Digitized stored voice paging receiver

An adaptive lock time controller for a phase locked loop having dividers for generating first and second loop timing signals, a phase detector, a voltage controlled oscillator, and a charging circuit for generating at least a first control signal for converging the output frequency to one or more predetermined frequency channels and a second control signal for maintaining the output frequency substantially constant, comprises a synchronization generator, a phase lock detector, and a control signal selector. The synchronization generator is responsive to the phase detector for synchronizing the phase lock detector. The phase lock detector detects phase locked and unlocked conditions by generating a count representative of the phase difference between the first and second loop timing signals. When the count generated exceeds a predetermined count, a phase locked condition exists, otherwise the loop is unlocked. The control signal selector selects the first control signal during the predetermined time interval when the phase unlocked condition is detected, and the second control signal when the phase locked condition is detected.

Adaptive lock time controller for a frequency synthesizer and method therefor

A frequency synthesizer (10) governed by a battery saving signal (20) having sleep and awake cycles (60, 62) comprises a phase locked loop and a control circuit (70) for enhancing the restart operation of the phase locked loop at the commencement of each awake cycle of the battery saving signal. More specifically, the phase locked loop includes a phase detector (26, 28) for locking the frequencies generated by a reference oscillator (12) and a voltage controlled oscillator (36) by adjusting a signal (38) in a storage device (34) used for governing the voltage controlled oscillator. During the sleep and awake cycles of the battery saving signal, the oscillators and phase detector are inhibited and enabled, respectively, in their operations. The control circuit is operative to inhibit the adjustment of the governing signal until both of the oscillators are determined to be effectively enabled at the commencement of each awake cycle of the battery saving signal to ensure the stored governing signal commences at its desired setting.

Frequency synthesizer with control of start-up battery saving operations

A dual bandwidth crystal controlled oscillator (200) is described having a first transconductance amplifier (202) providing sufficient gain to maintain oscillation with an oscillator crystal (210) at a minimum current drain. A second transconductance amplifier (218) is provided which can be selectively coupled to the first transconductance amplifier (202), thereby augmenting the gain of the first transconductance amplifier (202) to provide the capability for rapid oscillator start-up following battery saver operation. The dual bandwidth crystal controlled oscillator (200) can be utilized in conventional oscillator and frequency synthesizer applications.

Multiple bandwidth crystal controlled oscillator

A frequency synthesizer (fig. 1), which has at least one programmably characterized phase lock loop circuit (10, 14) includes a buffer memory (40, fig. 4) and an interface controller (38, fig. 2) responsive to operational codes received from a central controller (12) to direct transfer of data words (50, 52) for characterization of the phase lock loop circuit among the at least one phase lock loop circuit, the buffer memory, and the central controller. In one embodiment, the transfer of data words between the central controller and phase lock loop circuit or buffer memory are performed serially in accordance with a prespecified protocol and governed by a clock signal generated by the central controller. Data word transfers between the buffer memory and at least one phase lock loop circuit may also be performed serially in accordance with a prespecified protocol, but may be governed autonomously by an internal clock signal generated by the frequency synthesizer.

Omid Tahernia

Papers

Digitized stored voice paging receiver

Adaptive lock time controller for a frequency synthesizer and method therefor

Frequency synthesizer with control of start-up battery saving operations

Multiple bandwidth crystal controlled oscillator

Frequency synthesizer with an interface controller and buffer memory