Methods and devices supporting the management of a plurality of electronic devices and processing of update information for updating software and/or firmware in the electronic devices Prompting of users may be made using a language associated with the electronic device, and authorization to update an electronic device may be secured using a subscriber identity module

Device management in a network

Apparatus and methods for fault-tolerant computing using an asynchronous switching fabric where at least one of a plurality of redundant data processing elements executing substantially identical instructions communicates transactions to at least one target device, such as input/output device, or another data processing element. The transactions are communicated through the asynchronous switching fabric wherein each of the data processing elements and the target device are connected to the asynchronous switching fabric through a respective channel adapter.

Apparatus and methods for fault-tolerant computing using a switching fabric

The inventive system essentially hides redundant paths to the peripheral devices from the operating system, by reporting a single virtual path to the peripheral busses over PCI bus 0. The virtual path includes at least a virtual peripheral bus controller and a virtual video controller. The system also tells the operating system that the real controllers are on another PCI bus on an opposite side of a PCI-to-PCI bridge connected also to PCI bus 0. An I/O system manager selects one of the actual paths, which may, but need not, be connected to PCI bus 0, to handle communications with the peripheral devices. The I/O system manager maintains the controllers on the unselected path in an off-line or standby mode, in case of a failure of one or more of the controllers on the selected path. If a failure occurs, the I/O system manager performs a fail-over operation to change the selection of controllers, and the peripheral devices continue to operate in the same manner on the peripheral busses. The operating system does not respond to the controller failure by declaring a system failure, however, because the operating system continues to look to the virtual path, with its virtual controllers, as a valid path to the peripheral devices. The system also allows hot swapping of PCI bridges, through FET isolation of the unselected controllers. The devices on the PCI bus and the peripheral busses may also be hot swapped through selective FET isolation.

System and method for operating a system with redundant peripheral bus controllers

A device and system supporting installation of updates to software and/or firmware in memory of an electronic device. The updates may be accompanied by advertising, promotional and information content that is dynamically displayed to a user during processing of the update in the electronic device.

User experience and dependency management in a mobile device

The present invention relates to a method and system for transferring portions of a memory block. A first data mover is configured with a first start address corresponding to a first portion of a source memory block. A second data mover is configured with a second start address corresponding to a second portion of the source memory block sized differently from the first portion. The first portion of the source memory block is transferred by the first data mover and the second portion of the source memory block is transferred by the second data mover.

Method and apparatus for efficiently moving portions of a memory block

A data transfer controller transfers data in blocks having a restricted set of permitted sizes. Before transferring each block, the data transfer controller performs a segmented comparison on the current data address, at which the block starts, and a stopping address, at which the entire data transfer will end, and determines the block size from the result of the segmented comparison. In the segmented comparison, the data transfer controller compares a first part of the data address with a first part of the stopping address, then compares a second part of the data address with a second part of the stopping address. The comparison of second parts is made in different ways, depending on the result of the comparison of first parts.

Data transfer methods and controller for transferring data in blocks without crossing certain address boundaries

A bus arbitration system uses different arbitration rules at different times, by periodically changing the priority order of the bus masters; by masking further bus requests from a particular bus master for a certain interval each time that bus master is granted the use of the bus; by masking requests from bus masters other than a central processing unit for certain intervals while the central processing unit is processing an interrupt; by raising the priority of a particular bus master if a bus request from that bus master remains unacknowledged for a certain interval; or by ignoring bus requests from the central processing unit while another bus master is performing a certain process.

Bus arbitration system with changing arbitration rules

PROBLEM TO BE SOLVED: To easily secure the fairness in a bus usage right by preventing a bus from being too much occupied by any specified bus master by exchanging the priority between plural bus masters at every prescribed time. SOLUTION: A bus controller 5 is provided with a counter 61 for repeatedly updating a counted value synchronously with a clock signal and a priority information storage part 62 for storing four sets of priority information for exchanging the priority of bus usage rights among bus masters corresponding to the respective counted values of the counter 61, and selecting one set of priority information to be used for arbitrating the bus usage right out of these four sets of priority information while switching it at each clock.

Bus usage right arbitration system

PROBLEM TO BE SOLVED: To restrict a print image data read out rate below a generation rate thereof storing a page of print image data while compressing in a compressed data buffer, decompressing the compressed data upon start of printing and delivering the data from a data transfer section to a print section in synchronism the print operation. SOLUTION: A CPU 1 generates a band of image data being printed at first and stores that data in the band buffer of an RAM 4. When a band of image data is generated, it is compressed and stored in a compressed data buffer. Subsequently, the compressed data is transferred to a print control section 6 in a DMA 5 where the compressed data is decompressed at a decompressing section 6A and a data recovered to original image data is stored in a line buffer 6B. A data transfer section 6C outputs that image data to a print section 10 in synchronism the print operation. According to the arrangement, no space appears in the data even if the generation rate of next image data does no catch up the read out rate of compressed data.

Print data generator

A memory system includes a plurality of output buffers each of which outputs one of a plurality of one-bit signals forming data. The output buffers are put into a plurality of buffer groups. The memory system further includes a controller for feeding timing signals to the corresponding buffer groups via delay circuits having mutually different time constants, respectively. The timing signals include certain timing which causes the output buffers to output the corresponding one-bit signals. Since the foregoing certain timing is delayed depending on the time constants of the delay circuits, although the output buffers in the same buffer group output the corresponding one-bit signals simultaneously, the output buffers in the different buffer groups output the corresponding one-bit signals with mutually different timing.

Osamu Ishikawa

Papers

Data transfer methods and controller for transferring data in blocks without crossing certain address boundaries

Bus arbitration system with changing arbitration rules

Bus usage right arbitration system

Print data generator

Data output system