An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A method for data storage in a memory that includes a plurality of analog memory cells includes storing data in the memory by writing first storage values to the cells. One or more read reference levels are defined for reading the cells, such that at least one of the read reference levels is negative. After storing the data, second storage values are read from the cells using the read reference levels, so as to reconstruct the stored data. In another disclosed method, data is stored in the memory by mapping the data to first storage values selected from a set of the nominal storage values, and writing the first storage values to the cells. The set of nominal storage values is defined such that at least one of the nominal storage values is negative.

Memory device with negative thresholds

The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Semiconductor Integrated Circuit Device

A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

A circuit which monitors the internal state of flash memory array programming circuitry and conveys that state to circuitry external to the flash memory array so that external circuitry need not delay during any period in which a programming operation is taking place within the flash memory array.

Apparatus for determining the conditions of programming circuitry used with flash EEPROM memory

A potential detecting circuit comprises a first MOS transistor of a first conductivity type whose drain receives an input potential that is equal to or lower, in absolute value, than a second potential whose absolute value is higher than that of a first potential, a second MOS transistor of a second conductivity type whose source is connected to the source of the first transistor and gate receives the first potential, a third MOS transistor of the first conductivity type whose source is connected to the second MOS transistor, source receives a reference potential whose absolute value is lower than that of the first potential, and gate receives the first potential, a detecting potential control block for applying to the first MOS transistor a potential varying in accordance with the input potential, and a potential detect output terminal for providing a detected potential, the potential detect output terminal being a junction between the drains of the second and third MOS transistors.

Potential detecting circuit

The end cutting edge (6a) and corner blade (6b) of throw away tip (5) have differing curvature radius. The peripheral cutting edge (6c) of a linear blade is arranged adjacent to the corner blade. The curvature radius (R1) of the end cutting edge is made larger than the diameter of the inscribing circle or the length of the long side of the throw away tip. The blade ridge line of the peripheral cutting edge forms a certain angle with the axial direction of the tool body

Blade tip exchange type cutting tool for carving processing of metal die, has curvature radius of end cutting edge made larger than diameter of inscribing circle or length of long side of throw away tip

An ultrasonic wire bonder includes first and second ultrasonic wave applying devices, the direction of vibration of the first ultrasonic wave being orthogonal to that of the second ultrasonic wave. One of the first and second ultrasonic waves or a composite ultrasonic wave thereof is applied to a capillary and/or a support base for wire bonding, depending upon the bonding direction along which a wire is extended, or the inner lead longitudinal direction. A unit for detecting the positions of a semiconductor chip and lead frame may be provided to adjust a position and control the ultrasonic wave to be applied.

Ultrasonic wire bonder

A spare decoder has a first register, a second register, and a multiplexer for selecting the output of the first register or that of the second register. The first register stores data of a fuse element. In the ordinary operating mode, a defective memory cell is replaced by a spare cell in accordance with the data stored in the first register. In the test mode, it is determined whether at least one spare cell is defective or not. If there are no defective spare cells, the data that should be stored in the defective memory cell is written into one of the spare cells. Further, the address of the defective memory cell is written into the second register. The defective memory cell is replaced by one of the spare cells in accordance with the data stored in the second register, by cutting the fuse element in accordance with the address of the defective memory cell.

Semiconductor memory device having both redundancy and test capability and method of manufacturing the same

A memory cell of a nonvolatile semiconductor memory device includes a P conductive type semiconductor substrate, first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode formed on the channel region, and a control gate electrode formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.

Osamu Matsumoto

Papers

Potential detecting circuit

Blade tip exchange type cutting tool for carving processing of metal die, has curvature radius of end cutting edge made larger than diameter of inscribing circle or length of long side of throw away tip

Ultrasonic wire bonder

Semiconductor memory device having both redundancy and test capability and method of manufacturing the same

Nonvolatile semiconductor memory device with a double gate structure