A method of optimizing production of semiconductor devices on a wafer comprises steps of characterizing at least one effect of at least one manufacturing component on at least one optimization criterion; inputting user optimization data; and, based on the at least one effect and the user optimization data, performing optimization to determine a layout of semiconductor devices on the wafer that optimizes performance according to the user optimization data.

Optimization of die placement on wafers

In the manufacturing process of a semiconductor integrated circuit device, a plurality of identification elements having the same arrangement are formed and the relation of magnitude in a physical amount corresponding to variations in the process of the plurality of identification elements is employed as identification information unique to the semiconductor integrated circuit device.

Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip

A semiconductor structure includes a first semiconductor die and a second semiconductor die identical to the first semiconductor die. The first semiconductor die includes a first identification circuit; and a first plurality of input/output (I/O) pads on the surface of the first semiconductor die. The second semiconductor die includes a second identification circuit, wherein the first and the second identification circuits are programmed differently from each other; and a second plurality of I/O pads on the surface of the second semiconductor die. Each of the first plurality of I/O pads is vertically aligned to and connected to one of the respective second plurality of I/O pads. The second semiconductor die is vertically aligned to and bonded on the first semiconductor die.

Design techniques for stacking identical memory dies

A serialization service module is provided for configuring an asset management system to provide a secure means of generating, assigning to chips (or other electronic objects or devices), and tracking unique serial numbers. To provide this service, a controller is used to define a product model, then to define one or more serialization schemas to be bound to each product model. Each serialization schema contains a range of serial numbers for a particular product. The serial number schemas are sent over a secure, encrypted connection to appliances at the manufacturer's location. Agents can then request serial number values by product name. The serial numbers are generated by the appliance, metered, and provided to the agents. The serial numbers are then injected sequentially into each die in a chip manufacturing process using the agent.

System and method for performing serialization of devices

A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Clock generator with programmable non-overlapping-clock-edge capability

A method for manufacturing multi-kind and small-quantity semiconductor products in a mass-production line and a system thereof are provided. One aspect of the present invention, there is provided the method for manufacturing a semiconductor device through a plurality of fabrication processing steps, each of the fabrication processing steps being carried out sequentially with a plurality of chips on a wafer based on a chip identification information formed on the wafer, the method comprises at least two steps sharing the chip identification information before at least one of the two steps is carried out, wherein the steps are not immediately neighbored with each other in fabrication processing sequence.

Method for manufacturing multi-kind and small quantity semiconductor products in a mass-production line and system thereof

A CMOS Schmitt-trigger circuit for shaping the wave form of an input signal to be applied to logic circuits, such as flip-flops, counters, etc. The CMOS Schmitt-trigger circuit has an input terminal connected to a signal source, and comprises a first CMOS inverter, a second CMOS inverter connected in cascade to the first CMOS inverter, a third CMOS inverter connected in cascade to the second CMOS inverter, and a feedback resistance connected between the output end of the third CMOS inverter and the input end of the second CMOS inverter. The schmitt width of the CMOS Schmitt inverter according to the present invention has less dependency on the impedance of the input signal source than the prior-art devices do.

Cmos schmitt-trigger circuit

In order to improve the operable frequency of a programmable counter circuit which serves as an N-step counter by loading an initial value N, load terminals of flip-flops of respective stages forming the counter circuit are sequentially cascade-connected via buffers and a load signal is applied to each of the load terminals from a load signal generator circuit. The load signal generator circuit includes a detector circuit which detects a specified value which is provided a short time before the initial value loading of the counter circuit and generates a detected output signal. The detected output signal is shifted by a shift register included in the load signal generator circuit which operates on the same clock signal as that which drives the counter circuit, thereby generating the load signal at the moment of the initial value loading of the counter circuit. In this case, for the duration of the load signal and a certain period of time subsequent thereto the application of the output from the detector circuit to the shift register is inhibited by a load control circuit included within the load signal generator circuit, thus preventing erroneous loading.

Programmable counter circuit

PURPOSE:To increase the operating frequency of a program counter to the operation limit of flip-flop, by using the merit of the counter circuit interposing the buffer on the signal line for load signal supply. CONSTITUTION:A specific count value detection circuit DET detects the specific value a little before the calculation value when the initial value loading of the counter circuit is made. A shift register SHR receives the detected output of the circuit DET with the same clock as the clock driving the counter circuit and makes a shift and the load signal is produced at the time when the initial value loading of the counter circuit is made. A load control circuit LCT transmits a signal which inhibits the input of the output of circuit DET to the register SHR for the continuous period of load signal and a given period after that.

Program counter circuit

PURPOSE: To utilize effectively a conventional operating area being easily an idle area by constituting four corners of a rectangular chip as the conventional operating area and integrating the logical circuit of a Schmitt trigger circuit in this area. CONSTITUTION: The master slice type semiconductor circuit device 1 consists of plural logical cell arrays 2, plural input/output cells 3∼6, a power terminal 7 and wiring areas 8, 9, and the conventional operating area 10 exists at the four corners of the device 1. The logical circuit is integrated in the conventional operating area 10. The logical circuit is the Schmitt trigger circuit. That is, an inverter 14, two-input NAND circuits 15, 16 are integrated. Moreover, an input terminal IN in the area and an output terminal OUT in the area are connected electrically to a pattern in the wiring area 8 and/or 9. Thus, the constitution of the desired logical circuit is attained in the conventional operating area 10 in this way and the cell in the logical cell array 2 is utilized efficiently. COPYRIGHT: (C)1985,JPO&Japio

Osamu Takagi

Papers

Method for manufacturing multi-kind and small quantity semiconductor products in a mass-production line and system thereof

Cmos schmitt-trigger circuit

Programmable counter circuit

Program counter circuit

Master slice type semiconductor circuit device