A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

A semiconductor apparatus includes: a first insulating layer formed on an IC chip; a metal wiring having one end connected to a chip electrode pad, and one other end on which an external connection terminal mounting electrode is provided; an electronic component connected to part of the external connection terminal mounting electrode; an external connection terminal, which is made of a conductive material, formed on one other part of the external connection terminal mounting electrode; a second insulating layer covering, at least, (a) part of the external connection terminal mounting electrode to which the electronic component is not mounted, and (b) the metal wiring; and a sealing resin for sealing the electronic component and the external connection terminal in such a manner that the external connection terminal is partially exposed so as to have an exposed portion. Thus, a semiconductor apparatus and a manufacturing method thereof are provided, each of which realizes a wafer-level CSP on which an electronic component is mounted in such a manner that the electronic component is mounted on re-wiring, wherein the external connection terminal is (i) prevented from being deformed after mounted on the IC chip, from being decreased in height, and from being expanded to a horizontal direction; and (ii) formed with a fine pitch from another external connection terminal located adjacent from the external connection terminal, so that the wafer-level CSP is highly functional and has a large number of pins.

Semiconductor device and manufacturing method thereof

Disclosed is a method for configuring transmission antenna groups in a mobile communication system with multiple transmission antennas and multiple reception antennas. The method includes the steps of: receiving a first matrix having a size of ‘N t ×N t ’, which corresponds to N t number of transmission antennas, fedback from the mobile terminal, generating combinations of sub-matrixes of the first matrix corresponding to N r number of reception antennas, and calculating sums of maximum eigenvalues; determining combinations of the sub-matrixes having a maximum value from among the calculated sums of eigenvalues to be transmission antenna groups for the N t number of transmission antennas; and transmitting different relevant symbols from each other through the transmission antenna groups.

Method for grouping transmission antennas in mobile communication system including multiple transmission/reception antennas

An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.

Fabrication procedure for a stable post

PURPOSE:To avoid any film loss of a metallic film to be a wiring by a method wherein, after forming the metallic film for a metallic wiring with electrolytic plating process, an insulating film is formed only on this metallic film and then a conductive film used as a current channel is etched away using this insulating film as a mask. CONSTITUTION:A conductive film comprising a titanium film 12 and a platinum film 13 is formed on a lower layer insulating film 11 formed on a semiconductor substrate. Next, a photoresist 14 is formed and then patterned to form an opening 17 for wiring. After baking process, a gold film 15 thinner than the resist film 14 is formed in the opening 17 with electrolytic plating process. Next, a spin on glass film 16 such as PSG, etc., is formed on the whole surface and after performing the baking process at around 100 deg.C, the spin on glass film 16 is left only on the gold film 15 with etching back process. Next, the resist film 14 is removed by plasma processing in O2. Next, the platinum film 13 and the titanium film 12 formed into the conductive film are removed using the spin on glass 16 on the gold film 15 as a mask. Finally, the spin on glass film 16 is removed thereby enabling a wiring comprising the no-film loss gold film 15 to be formed.

Manufacture of semiconductor device

PURPOSE:To form high melting point metal silicide with a better close adhering ability on a diffusion layer for source and drain regions of a MOS device, by forming a gate electrode, by depositing silicide, and by etching the silicide portion having silicon underlaid by using a mask of a silicon oxide film. CONSTITUTION:On the surface of a silicon substrate 11, a field oxide film 12, gate oxide film 13, polycrystalline silicon layer 14 and polycrystalline silicon gate electrode 14' are formed. After a CVD-SiO2 film is formed over the entire face, reactive ion etching forms side walls 15. Next, an N diffusion layer 16 is formed, high melting point metal silicide 17 is formed over the entire face, and then thermal oxidation forms a silicon oxide film 18. Thereafter, the portion of the silicon oxide film 18 under which there does not exist silicon is removed, only the silicon oxide film 18 on the diffusion layer 16 for the source and drain regions and on the gate electrode 14' is left, and the silicide 17 is etched using a mask of this silicon oxide film 18. Next, a PSG film 19 is evaporated, contact holes 20 are formed, and an Al film is evaporated over the entire face and is patterned to form Al wiring 21.

PURPOSE:To ensure the breakdown strength of an n-channel MISFET by making an insulating film on the sidewall of a p-channel MISFET smaller than that on the sidewall of the n-channel MISFET in a semiconductor integrated circuit device with a CMOS adopting LDD structure. CONSTITUTION:Length in the channel length direction of a semiconductor region 18 is constituted in size smaller than semiconductor regions 9 in a MISFETQn and a MISFETQS. That is, a sidewall insulating film 19 is organized so that length in the channel length direction is made smaller than a sidewall insulating film 16 in the MISFETQn and a sidewall insulating film 10 in the MISFETQS. The sidewall insulating film 19 is constructed in size smaller than 0.3mum such as 0.1mu-0.25mum on a 1.3mum process. That is, since the series resistance value of a semiconductor region (between a source region and a drain region) 20 can be lowered, current driving force can be increased while a section (between a source region and a drain region) between semiconductor regions 17 can be isolated, thus ensuring breakdown strength between the semiconductor regions 17.

Semiconductor device and manufacture thereof

PURPOSE:To prevent a threshold value of a transistor for constituting a peripheral circuit from being decreased undesirably by forming source and drain regions of said transistor after formation of a memory cell CONSTITUTION:DRAM consists of a memory cell region 1 and a peripheral circuit region 2 formed on a P type semiconductor substrate 3 In order to produce such DRAM, P- and N type well regions 4, 5 are formed on the substrate 3 and then gate electrodes 10, 28, 31, 32 are formed thereon Then, the region 2 is totally covered with a mask The memory cell consisting of a selective MISFET Qi and a stacked storage capacity Ci is formed in the region 1 After the mask on the region 2 is removed, source and drain regions 26, 27, 29, 30 are formed in the regions 4, 5 within the region 2 According to such a method, the regions 26, 27, 29, 30 have junctions shallower than those of the regions 8, 9 Accordingly, the threshold value of the element in the region 2 is not decreased undesirably

Otsuka Fumio

Papers

Manufacture of semiconductor device

Semiconductor device and manufacture thereof

Semiconductor storage device and manufacture thereof