The authors describe automatic architecture and floorplan generation techniques for integrated circuit fixed-coefficient FIR (finite impulse response) filters that can achieve high sample rates with compact layouts. These techniques have been implemented in a filter design system called FIRGEN that can automate the entire design from filter specifications to final chip layout. It can be retargeted to new cell libraries and place and route tools. Result on four chips designed with FIRGEN are presented. These achieve sample rates ranging from 25 MHz to 112 MHz. >

FIRGEN: a computer-aided design system for high performance FIR filter integrated circuits

A design methodology for automated mapping of DSP algorithms into VLSI architectures is presented. The methodology takes into account explicit algorithm requirements on throughput and latency, in addition to VLSI technology constraints on silicon area and power dissipation. Algorithm structure, design style of functional units, and parallellism of the architecture are all explored in the design space. The synthesized architecture is a multibus multifunction unit processor matched to the implemented algorithm. The architecture has a linear topology and uses a lower number of interconnects and multiplexer inputs compared to other synthesized architectures with random topology having the same performance. The synthesized processor is a self-timed element externally, while it is internally synchronous. The methodology is implemented in a design aid tool called SPAID. Results obtained using SPAID for two DSP algorithms compare favorably with other synthesis techniques. >

Architectural synthesis for DSP silicon compilers

The origin of anti-infective therapy in the Western hemisphere dates back to the use of cinchona bark to treat malaria by the indigenous peoples in South America. This discovery was taken to Europe in the seventeenth century. These observations were used to develop the drug quinine, which is still used in the treatment of malaria today. The Chinese have a 5,000 year history of using herbal remedies that may still lead to new anti-infective agents.

Introduction and History

Tradeoffs in the design of the timing recovery functions in a subscriber loop receiver are analyzed. The techniques considered are applicable to both the echo cancellation (EC) and time compression multiplexing (TCM) methods of full duplex transmission. Emphasis is on those techniques that lend themselves to implementation in MOSLSI technology, where the objective requirement is that timing recovery be implemented on a sampled-data signal (with the minimum possible sampling rate where EC is used). The wave difference method (WDM) for timing recovery appears to be the best candidate. A detailed study of its performance is carried out analytically and by computer simulation for the case of binary and alternate mark-inversion (AMI) line coding. A closed form expression describing the binary jitter performance of the WDM and its continuous time counterpart, the spectral line technique, is used to compare the two techniques. Analytical and simulation results for recovered phase and jitter are presented for various cable pulse responses carefully chosen to represent worst-case or nearly worst-case conditions. Two methods for including frequency detection in the WDM, the quadricorrelator and the rotational detector, are also simulated.

/pdf/timing-recovery-in-digital-subscriber-loops-4ncjpzus4e.pdf

Timing Recovery in Digital Subscriber Loops

http://ieeexplore.ieee.org/iel5/5468216/5468217/05468267.pdf

Silicon Compilation

In order to reduce the design time of digital filter bank circuits, a design system has been developed. The software consists of the filter compiler which converts high level filter descriptions to hardware descriptions and the layout generator which converts the hardware descriptions to a layout file. To verify the algorithms before fabrication, a test system is employed. The development time of this system was kept to a minimum by designing the hardware to be easily micro coded and assembled. Several circuits have been fabricated and tested that were generated with this system, including a single bandpass filter chip, a 112-pole 16-channel filter bank for a speech recognition system and a 16-channel spectrum analyzer for consumer stereo applications. The speech recognition chip achieved a SNR of 80 dB with an area of 25 mm /sup 2/ in a 4-micron NMOS technology.

P.A. Ruetz

Papers

Computer Generation of Digital Filter Banks