Power and RF electronics applications have spurred massive investment into a range of wide and ultrawide bandgap semiconductor devices which can switch large currents and voltages rapidly with low losses. However, the end systems using these devices are often limited by the parasitics of integrating and driving these chips from the silicon complementary metal–oxide-semiconductor-based design (CMOS) circuitry necessary for complex control logic. For that reason, implementation of CMOS logic directly in the wide bandgap platform has become a way for each maturing material to compete. This review examines potential CMOS monolithic and hybrid approaches in a variety of wide bandgap materials.

Prospects for Wide Bandgap and Ultrawide Bandgap CMOS Devices

An overview is presented of the significant influences of Moore’s Law scaling on radiation effects on microelectronics, focusing on historical trends and future needs. A number of milestones in the evolution and understanding of total-ionizing-dose and single-event effects are discussed within the context of classical Dennard scaling. This discussion focuses on the discovery of fundamental mechanisms, development of radiation-tolerant IC technology, and increasing maturity and complexity of Si-MOS-based devices, circuits, and systems. Examples are shown that illustrate how the end of Dennard scaling has influenced radiation effects in current technology generations, due to the increasingly complex and diverse materials and devices that are now incorporated. The radiation responses of devices with alternative channels to silicon and transistors based on 2-D materials are discussed, with an emphasis on opportunities and challenges for ultimately scaled devices. Particular challenges to ultimately scaled technologies are presented by single-particle-induced displacement damage and microdose effects. The article concludes with a look forward to a future in which many types of microelectronic devices and ICs are increasingly more vulnerable to radiation effects and increasingly more difficult to test in a practical and cost-effective manner.

Radiation Effects in a Post-Moore World

The next decade will usher in a new era of technological innovation where compute, communications, and intelligence will converge. The number of connected devices is estimated to reach 500 billion by 2030, which is 59× larger than the expected world population [1] . Instead of humans dominating the use of wireless networks, objects or things will become the dominant users. Networks will incorporate intelligent compute to enable new types of applications such as cyberphysical worlds that replicate reality. These applications will require distributed intelligent compute platforms, as processing terabytes of data at a single edge device will be near impossible. Future 6G systems are currently being defined to meet these needs, as shown in Figure 1 , and the essential components of all 6G systems will be intelligence and security [2] . These new wireless systems will need to leverage a distributed compute network that is part of the wireless network so that the edge device can employ a high-performance compute platform that is in close proximity to itself. Such a network device must incorporate flexibility and programmability at low latency while also supporting network and connectivity functions. Heterogeneous integration in 2.5D and 3D can efficiently enhance existing compute platforms such as processors, application-specific integrated circuits, and field programmable gate arrays (FPGAs) to address emerging applications such as intelligent compute-communicate systems at lower cost with faster time to market. This article presents an overview of 2.5D and 3D heterogeneous technologies and how they can be leveraged to create new intelligent-compute-communicate platforms to enable emerging applications

2.5D and 3D Heterogeneous Integration: Emerging applications

Integrated circuits (ICs) and optoelectronic chips are the foundation stones of the modern information society. The IC industry has been driven by the so-called “Moore’s law” in the past 60 years, and now has entered the post Moore’s law era. In this paper, we review the recent progress of ICs and optoelectronic chips. The research status, technical challenges and development trend of devices, chips and integrated technologies of typical IC and optoelectronic chips are focused on. The main contents include the development law of IC and optoelectronic chip technology, the IC design and processing technology, emerging memory and chip architecture, brain-like chip structure and its mechanism, heterogeneous integration, quantum chip technology, silicon photonics chip technology, integrated microwave photonic chip, and optoelectronic hybrid integrated chip.

Recent progress of integrated circuits and optoelectronic chips

We demonstrate industry’s first 300 mm GaN transistor technology and 3-D monolithic heterogeneous integration with Si transistors, enabled by 300 mm GaN metal–organic chemical vapor deposition (MOCVD) epitaxy and 300 mm 3-D layer transfer. The 300 mm GaN technology is a high- ${k}$ dielectric enhancement-mode GaN nMOS transistor technology on Si(111) substrate. It is capable of excellent characteristics and figure-of-merits (FOM) for realizing energy-efficient, compact power-delivery and RF front-end components such as power-amplifiers, low-noise amplifiers, and RF-switches. Our GaN nMOS transistors show e-mode operation with: 1) high ${I}_{\text {D,max}} =1.5$ mA/ $\mu \text{m}$ ; 2) low ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of $610\,\,\Omega -\mu \text{m}$ ( ${L}_{\text {G}} =50$ nm); 3) low ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ of 100 pA/ $\mu \text{m}$ ( ${L}_{\text {G}} \,\,=180$ nm), which are significant improvements over GaN HEMT; 4) excellent RF performance: ${f}_{\text {T}} =190$ GHz, ${f}_{\text {MAX}} =300$ GHz, power-added efficiency (PAE) = 56% ( ${L}_{\text {G}} \,\,=50$ nm) at mmwave frequency 28 GHz, and PAE = 77% at 5 GHz ( ${L}_{\text {G}} =180$ nm), significantly better than industry-standard GaAs and Si RF transistors; 5) good RF-switch FOM, ${R}_{ \mathrm{\scriptscriptstyle ON}}{C}_{ \mathrm{\scriptscriptstyle OFF}} =110$ fs; and 6) low noise figure, NF $_{\text {min}} \,\,=1.36$ dB ( ${f} =28$ GHz) and 0.4 dB ( ${f} =5$ GHz), all at SoC-compatible voltages. We further demonstrate GaN transistor innovations all integrated on 300 mm Si(111) wafer, including depletion-mode GaN nMOS transistor with high ${I}_{\text {D}} =1.8$ mA/ $\mu \text{m}$ ; GaN Schottky gate transistor producing high saturated power of 20 dBm ( $80\mu \text{m}$ width) with peak PAE = 57% at 28 GHz; low leakage compact cascode and multigate GaN transistors; and GaN Schottky diodes with ultralow ${C}_{ \mathrm{\scriptscriptstyle OFF}}$ for electrostatic discharge (ESD) protection. The layer-transferred Si transistors, monolithically stacked on top of the GaN transistors by 300 mm 3-D layer transfer, show high drive current performance: 1.0 mA/ $\mu \text{m}$ (Si nMOS) and 0.5 mA/ $\mu \text{m}$ (Si pMOS). Such a monolithic 3-D Monolithic integration of GaN and Si transistors enables full integration of energy-efficient, truly compact power delivery and RF solutions with CMOS digital signal processing, logic computation and control, memory, and analog circuitries.

Gallium Nitride and Silicon Transistors on 300 mm Silicon Wafers Enabled by 3-D Monolithic Heterogeneous Integration

We have demonstrated industry’s first 300mm 3D heterogeneous integration of high performance, low-leakage high-K dielectric metal gate enhancement-mode (e-mode) GaN NMOS and Si PMOS transistors on 300mm high-resistivity (HR) Si(111) substrate, enabled by 300mm GaN MOCVD epitaxy and 300mm 3D layer transfer. The fabricated (bottom device layer) high-K dielectric e-mode GaN NMOS transistors, integrated on a 300mm HR Si(111) substrate, show excellent electrical characteristics and figure-of-merits (FOM) for realizing energy-efficient, compact voltage regulators and RF front-end components such as power amplifiers, low-noise amplifiers and RF switches, with (i) I OFF as low as 100pA/μm (V D =5V, V G =0V), (ii) high I D,max =1.5mA/μm; (iii) R ON as low as 610Ω-μm, significantly better than industry-standard Si transistors at equivalent drain breakdown (BV D ), (iv) excellent RF performance: f T =190GHz, f MAX =300GHz, PAE=56% at mmwave frequency (f=28GHz), and PAE=70% at sub-7GHz (f=5GHz), significantly better than industry-standard GaAs and Si RF transistors, (v) excellent RF switch FOM, R on C off =110fs, and (vi) low noise figure, NF min =1.36dB (f=28GHz), 0.4dB (f=5GHz) and 0.27dB (f=1.8GHz), all at SoC-compatible voltages. The fabricated (top device layer) L G =65nm and 130nm Si PMOS transistors, which are monolithically integrated on top of the bottom GaN NMOS transistors by 300mm 3D layer transfer, show respectively, high drive current of 0.85mA/μm, and low I off of 150pA/μm at V D =-1.2V. Such a monolithic 3D integration of GaN NMOS and Si PMOS enables full integration of energy-efficient, truly compact power delivery and RF solutions with CMOS digital signal processing, logic computation and control, memory functions and analog circuitries for next generation power delivery, RF (5G and beyond) and SoC applications.

3D heterogeneous integration of high performance high-K metal gate GaN NMOS and Si PMOS transistors on 300mm high-resistivity Si substrate for energy-efficient and compact power delivery, RF (5G and beyond) and SoC applications

We expand on our work in [1] by demonstrating both Si P- and NMOS finfet transistors monolithically integrated with GaN transistors on 300mm Si(111) wafers using 3D integration. With the Si finfet architecture, we are able to take advantage of the fin orientations of the transferred Si(100) crystal to fabricate both high performance Si P- and NMOS transistors. Furthermore, we demonstrate a variety of GaN transistor innovations, including enhancement (e-mode) and depletion mode (d-mode) GaN NMOS transistor with high $\mathrm{I}_{\mathrm{D}}=1.8\mathrm{m}_{1}\mathrm{W}\mu \mathrm{m};\mathrm{GaN}$ Schottky gate transistor producing high saturated power of 20dBm with peak PAE=57% at 28GHz; high performing, low leakage cascode and multi-gate GaN transistors; and GaN Schottky diodes with ultra-low $\mathrm{C}_{\mathrm{OFF}}$ for ESD protection, all integrated on 300mm Si(111) wafer.

P. Agababov

Papers

3D heterogeneous integration of high performance high-K metal gate GaN NMOS and Si PMOS transistors on 300mm high-resistivity Si substrate for energy-efficient and compact power delivery, RF (5G and beyond) and SoC applications

GaN and Si Transistors on 300mm Si(111) enabled by 3D Monolithic Heterogeneous Integration