A unified discrete cosine transform and inverse discrete cosine transform (DCT/IDCT) architecture is used in the design of a proposed single-chip VLSI implementation of this function. An 8-point by 1 organization of the DCT/IDCT is chosen to allow easy implementation of the 8 × 8 format under consideration for recommendation by the International Consultative Committee for Telephone and Telegraph (CCJTT) for 384 K-bit CODECs. Fast DCT and IDCT algorithms are merged into a single hardware architecture that is programmable with a single DCT/IDCT selection switch. To accomplish real-time 10 MHz video data processing, the basic system clock brings data in and sends data out each 100 ns. Eight pixels are loaded for simultaneous processing every 800 ns and the module of each pipeline stage processes these eight elements simultaneously. Algorithm simulations and experimental performance of integrated test sub-circuit prototypes indicate that this proposed new DCT/IDCT chip would be capable of the real-time proces...

Unified forward and inverse discrete cosine transform architecture and proposed VLSI implementation

A unified discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) architecture suitable for VLSI implementation is presented. A single VLSI NMOS chip design and layout for realizing this architecture is described. Algorithm simulations and experimental performance of integrated test subcircuits indicate that this chip would be capable of real-time processing of 10-MHz video signals. It is considered that circuits of this type could be very useful in real-time image data compression. >

A unified DCT/IDCT architecture for VLSI implementation

Advantages of multiple-valued logic (MVL), such as reduced numbers of signal lines and increased functional density, are often accompanied by the disadvantage of reduced raw speed of operation. In some design situations, clock and throughput speeds are set by the application or design strategy. In such a situation, it may be possible to exploit the advantages of MVL without incurring the speed penalty. In this paper, we describe the design of a pipelined mathematical transform chip that can use MVL circuitry without speed penalty, requiring approximately 175% less silicon area than an all-binary version. CMOS quaternary threshold logic circuits are used in the design of the instruction memory and multiplier sections of the proposed single-chip implementation of a unified discrete cosine transform/ inverse discrete cosine transform (DCT/IDCT) architecture. This proposed MVL CMOS DCT/IDCT chip is projected to be capable of real-time processing of 10MHz video signals. In this paper, the unified DCT/IDCT arch...

Application of quaternary logic to the design of a proposed discrete cosine transform chip

CMOS quaternary threshold logic circuits are used in the design of the instruction memory and arithmetic sections of a proposed single-chip implementation of a unified discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) architecture. The chip is projected to be capable of real-time processing of 10-MHz video signals. The unified DCT/IDCT architecture is described, and the use of quaternary logic circuits is discussed. A 17.5% area savings has been achieved. >

http://ieeexplore.ieee.org/iel2/204/272/00005146.pdf

A proposed DDT/IDCT chip design using quaternary logic

This paper proposes a unified architecture for computation of different Type I/II/III/TV discrete cosine/sine transforms (DCT/DST), modified discrete cosine transform (MDCT) and their inverses. Two methods are described, a parallel one suitable for any length of transform (N) value from 2 to 1024 and a serial one, that uses only one CORDIC up to a maximum length of 32.

Unified architectures for computing DCT/DST/MDCT and their inverses

A common architecture, which is based on the Cooley-Tukey[1] algorithm, is developed for the Fourier, Hadamard, and forward and inverse Cosine transforms. The theory to implement the first three transforms in this architecture is well known. However, the existing algorithms for the inverse Cosine transform (IDCT) would disqualify it from the unified architecture and this led us to develop a new IDCT algorithm which falls within the unified architecture if we allow ourselves the luxury of double length processing. Details of the unified architecture and the new algorithm for the IDCT will be given in this paper.

P. Farrelle

Papers

A unified transform architecture