Disclosed is a memory system capable of being integrated into a semiconductor substrate and having an array of Hi-C memory cells. The Hi-C cells are selectively addressable by row and column lines. Each cell of the array is comprised of a transistor having a source coupled to a bit line, a gate coupled to a word line, and a drain coupled to a node N. Node N is coupled in parallel to a dielectric capacitor and to a depletion capacitor. The dielectric capacitor and the depletion capacitor are constructed to have substantially the same charge capacity.

High capacity dynamic ram cell

Disclosed is a process for constructing an array of memory cells. Each cell is constructed to have a high storage capacity and low leakage current. The cells are formed on a surface of a semiconductor substrate. Each cell has a storage region and an adjacent transfer region. The process forms a deep ion layer and a shallow ion layer in the storage region of each cell. At the storage region-transfer region interface, the deep ion layer lies laterally within the shallow ion layer. In the other portions of the storage region, the deep ion layer extends laterally into adjoining channel stops.

Fabrication methods for the high capacity ram cell

An IGFET integrated circuit memory cell structure utilizing a capacitor with increased charge storage capability, and a method making the same. The capacitor includes a high impurity concentration region having the same conductivity type as the substrate. An island of opposite conductivity type is inset in the region and a conductive field plate overlies the island. The structure also includes a transfer transistor in which the source region is adjacent the capacitor and overlaps the island region therein. Activation of the transistor serves to transfer the charge stored in the capacitor to the drain region where it can be read by external circuitry. In the method, the high concentration region and island in the capacitor are formed by successive ion implantation steps. A subsequent source and drain diffusion causes lateral migration of the conductive portions of the cell to increase the storage capacitance and to insure electrical contact between the island region of the capacitor and the source of the transfer transistor.

IGFET Integrated circuit memory cell

In one example, a random access memory cell includes an MOS gating transistor to activate the cell for reading, writing, or refreshing data stored on a cell capacitor structure. A typical cell transistor includes P1 (input/output) and P2 (cell storage) diffusions in an N-type substrate, P2 serving as one terminal or plate of the cell capacitor structure. According to this application, a preferred cell capacitor is formed by diffusing an N+ region over a major portion of the P2 region and extending beyond the P2 region in electrical contact with the grounded N substrate. The primary cell capacitor is defined between the P2 diffusion, a depletion region induced at the P2-N+ junction when P2 is charged, and the grounded N substrate. The N+ diffusion also reduces an unwanted parasitic capacitance between the P2 region and a transistor gate conductor for the cell, reduces leakage currents and permits greater packing density of cells. More generally, the application relates to an improved semiconductor capacitor storage structure and method, including a substrate of one conductivity type, a first diffusion of the opposite type on the substrate and constituting one capacitor terminal, and a second diffusion of the substrate conductivity type covering most of the first diffusion and in electrical contact with the substrate, the second diffusion and substrate forming the second capacitor terminal. The dielectric of the capacitor storage structure is formed by a depletion region between the first diffusion and both the substrate and second diffusion.

Semiconductor capacitor structure and memory cell, and method of making

A semiconductor read/write memory comprised of an array of cells, each having a single active element that is a IGFET device formed in a recess with one source or drain region located directly above and its other source or drain region located within a buried storage capacitor. The gate of each device is connected to an address line in the array, and transverse diffused bit lines interconnect the drains of the devices in aligned and spaced apart cells. Voltage applied via an address line activates a gate to charge its buried capacitor and store a signal when its connected bit line is also activated. Readout of stored charges is controlled by the address line through the connected bit line in the conventional manner. A memory device with an array of such single element cells can be fabricated by forming an array of N-type buried layer diffusions in a P substrate, depositing an epitaxial layer of lightly doped P material that extends above the buried layer diffusions, forming a relatively thin diffusion of N material spaced directly above the buried layer, forming a recess that passes through the thin N layer and the epitaxial layer into the thicker buried N layer, and thereafter forming a gate within the recess.

Epitaxial method of fabricating single igfet memory cell with buried storage element

A dynamic data storage cell is disclosed that requires only one insulated gate field effect transistor (IGFET) to store binary data. The drain of the FET is connected to a data input line and data is stored at the source node of the transistor by the inherent capacitance between the source diffusion and the substrate. The capacitance of the source electrode is enhanced by forming a heavily doped layer to underlie a portion of the source diffusion. Using the substrate as circuit ground enables the fabrication of an array of transistors for a random access memory wherein the surface area of the semiconductor chip is minimized.

P Frandon

Papers

Dynamic data storage cell