For reasons of economy and flexibility, BISDN (Broadband Integrated Services Digital Network) is expected to replace existing application-oriented communication networks. ATM (Asynchronous Transfer Mode) is a high-speed packet-switching technique that has emerged as the most promising technology for BISDN. Since early 1980s, a large number of architectures have been proposed for ATM switching. In this paper, we present a descriptive survey of ATM switch architectures, with emphasis on electronic space-division point-to-point switches.

Survey of ATM switch architectures

A buffered crosspoint matrix of an asynchronous transfer mode (ATM) switch includes a plurality of switching elements (38) for receiving and switching segments containing ATM cells. Each switching element (38) receives segments at a plurality of multicast/routing elements (52) which generates insert enable signals for each segment to route segments to selected crosspoints of a plurality of vertical bar elements (54). Each vertical bar element (54) includes a plurality of queuing systems for receiving and storing segments within an associated common buffer area. Segments are prioritized according to class of service and segment locations within the common buffer area are stored in subqueues. Each queuing system performs a first phase contention resolution tournament to determine an oldest segment of those segments at the head of the subqueue list. An output selector performs a second phase contention resolution tournament by determining the most aged segment from the oldest segments within the queuing system.

Buffered crosspoint matrix for an asynchronous transfer mode switch and method of operation

This paper calls for rethinking packet-switch architectures by cutting all dependencies between the switch fabric and the linecards. Most single-stage packet-switch architectures rely on an instantaneous communication between the switch fabric and the linecards. Today, however, this assumption is breaking down, because effective propagation times are too high and keep increasing with the line rates. In this paper, we argue for a self-sufficient switch fabric by moving all the buffering from the linecards to the switch fabric. We introduce the crosspoint-queued (CQ) switch, a new buffered-crossbar switch architecture with large crosspoint buffers and no input queues, and show how it can be readily implemented in a single SRAM-based chip using current technology. For a crosspoint buffer size of one, we provide a closed-form throughput formula for all work-conserving schedules under uniform Bernoulli i.i.d. arrivals. Furthermore, we study the performance of the switch for larger buffer sizes and show that it nearly behaves as an ideal output-queued switch. Finally, we confirm our results using synthetic as well as trace-based simulations.

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The Crosspoint-Queued Switch

An integrated method for congestion control uses access regulator to control the admission of information from a communication device into a network according to a predetermined function characterized by a set of parameters. A node within the network sends a signal indicating a level of congestion in the the node to the access regulator, and at least one of the parameters is adjusted in response to the signal. The parameter may additionally be adjusted according to other parameters which which are selected according to stability and transient response criteria.

Method for integrated congestion control in networks

In this paper, queue designs for true fully adaptive routers are explored. The proposed DAMQWR and VCDAMQ designs are aimed at exploiting the full capabilities of adaptive routing. Their effects on overall network cost and performance are evaluated analytically and by simulation. We show that DAMQWR best supports true fully adaptive routing capability by dynamically and efficiently managing queue and network resources, resulting in the highest network performance. Results show that up to 20% higher throughput can be obtained in comparison to traditional DAMQ designs.

Evaluation of Queue Designs for True Fully Adaptive Routers

The authors present a queuing analysis and a simulation study of banyan switch fabrics based on 2*2 switching elements with crosspoint buffering. In particular, the results apply to the PHOENIX switching element based banyan fabrics. The results indicate that crosspoint buffering provides throughput approaching the offered load under uniform traffic conditions. The effect of bursty traffic on the performance of the switch is studied. It is shown that a speedup factor of three or more is required to achieve acceptable delay and packet loss probability. It is also shown that the amount of buffer space required per port increases linearly with the burst size for a desired packet loss performance. For a given burst size the packet loss rate decreases exponentially as the buffer size is increased. The impact of crosspoint buffering and shared buffering in the switching elements on the performance of the banyan fabric is analyzed. >

P. Goli

Papers

Performance of a crosspoint buffered ATM switch fabric