This paper presents a novel processor for the implementation of multiplierless FFT's in VLSI. The arithmetic scheme is specially tailored for the simple binary coefficients used for these FFT's, which make multiplication trivial. (The class of coefficients dealt with are those that have a maximum of 2 nonzero digits; i.e., sum of 2 integers powers of 2 with each power in the range 0-4.) A single chip processing element for a 4-point DFT (for a radix 4 FFT) with an execution time of 400 ns using a 10 MHz clock has been realized. The chip has an estimated maximum gate count of 11 000 and pin count of 85. It has the capability of achieving a 40 MHz throughput rate for a 1024-point FFT using 20 processing IC's. The use of the 4-point chip to implement higher radix algorithms and various other issues are discussed.

Architectures for multiplierless fast Fourier transform hardware implementation in VLSI

We present an unified parallel architecture for four of the most important fast orthogonal transforms with trigonometric kernel: Complex Valued Fourier (CFFT), Real Valued Fourier (RFFT), Hartley (FHT), and Cosine (FCT). Out of these, only the CFFT has a data flow coinciding with the one generated by the successive doubling method, which can be transformed on a constant geometry flow using perfect unshuffle or shuffle permutations. The other three require some type of hardware modification to guarantee the constant geometry of the successive doubling method. We have defined a generalized processing section (PS), based on a circular CORDIC rotator, for the four transforms. This PS section permits the evaluation of the CFFT and FCT transforms in n data recirculations and the RFFT and FHT transforms in n-1 data recirculations, with n being the number of stages of a transform of length N=r/sup n/. Also, the efficiency of the partitioned parallel architecture is optimum because there is no cycle loss in the systolic computation of all the butterflies for each of the four transforms. >

http://www.biblioteca.uma.es/bbldoc/articulos/16732789.pdf

Parallel architecture for fast transforms with trigonometric kernel

Complex rotators are used in many important signal processing applications, including Cooley-Tukey and split-radix FFT algorithms. This paper presents methods for designing multiplierless implementations of fixed-point rotators and FFTs, in which multiplications are replaced by additions, subtractions, and shifts. These methods minimise the adder-cost (the number of additions and subtractions), while achieving a specified level of accuracy. FFT designs based on multiplierless rotators are compared with designs based on the multiplierless implementation of DFT matrix multiplication. These techniques make possible VLSI implementations of rotators and FFTs which could achieve very high speed and/or power efficiency. The methods can be used to provide any chosen accuracy; examples are presented for 12 to 26 bit accuracy. On average, rotators are shown to be implementable using 10, 12, or 15 adders to achieve accuracies of 12, 16, or 20 bits, respectively.

/pdf/multiplierless-implementation-of-rotators-and-ffts-1443ibr9tm.pdf

Multiplierless implementation of rotators and FFTs

A Mixed Integer Linear Programming (MILP) technique for the optimal design of windowed FFTs with discrete coefficients is presented. The technique uses a frequency domain optimisation suitable for spectrum analysis applications. The complex coefficients are constrained to have real and imaginary components which are integer powers of two or the sum of two integer powers of two. This results in a multiplierless system with significant savings in time and hardware costs.

Optimal design of multiplierless DFTS and FFTS

In a previous paper it has been shown that the complex coefficients of a discrete Fourier transform (DFT) used in spectral analysis, can be replaced by an optimum set whose real and imaginary components are constrained to be integer powers of two or the sum of two integer powers of two thus making multiplication trivial. However, the technique used ruled out any further increase in speed and reduction in hardware cost by factorisation of the DFT. The scheme presented in the paper overcomes this drawback and is applicable to the Cooley-Tukey fast Fourier transform algorithm.

P.J.W. Rayner

Papers

Optimal design of discrete coefficient DFTs for spectral analysis: extension to multiplierless FFTs