Thin-film thermoelectric cooling is a promising technology for mitigating heat dissipation in high performance chips. In this paper, we present an optimization framework for an active cooling system that is comprised of an array of thin-film thermoelectric coolers. We observe a set of constraints of the cooling system design. Firstly, integrating an excessive amount of coolers increases the chip package cost. Moreover, thermoelectric coolers are active devices, which dissipate heat in the chip package when they are in operation. Hence, setting the supply current level to operate the cooler improperly can actually lead to overheating of the chip package. Besides, the supply current needs to be delivered to the integrated cooler devices via dedicated pins. However, extra pins available on high-performance chip packages are limited. Observing these constraints, we propose an optimization framework for configuring the active cooling system, which minimizes the maximum silicon temperature. This includes determining the amount of coolers to deploy and their locations, the mapping of supply pins to the coolers, and determining the current levels of each pin. We propose algorithms to tackle the optimal configuration problem. We found that only a small portion of the silicon die needs to be covered by TEC devices (18% on average). Our experiments show that our algorithms are able to reduce the temperatures of the hot spots by as much as 10.6 °C (compared to the cases without integrated thermoelectric coolers). The average temperature reduction is 8.6 °C when 4 dedicated pins are available on the package. The total power consumption of the resulting active cooling system is reasonably small (~ 2 W). Our experiments also reveal that our framework maximizes the efficiency of the cooling devices. In the ideal case where hundreds of pins are available to tune the supply level of each individual cooler, the additional average reduction of the hot spot temperature is only 0.3 °C.

A framework for optimizing thermoelectric active cooling systems

In this paper, we present a novel architecture for embedding bi-metallic thermocouple based temperature sensors into 3D IC stacks. To the best of our knowledge this is the first work addressing this specific integration problem. Our architecture uses dedicated vias to thermally couple sensors in the metal layer with the hotspots to be monitored in the active layer throughout the multi-stack structures. We propose a low cost solution by leveraging a fraction of existing thermal TSVs for this purpose. Through thermal modeling and simulation using a state-of-the-art tool (FloTHERM), we demonstrate that we can achieve high accuracy (less than 1°C error) in temperature tracking while still maintaining the effectiveness of the thermal TSVs in heat management (conforming to a fixed peak temperature threshold of 95°C).

Integrating thermocouple sensors into 3D ICs

We established a novel theoretical analysis framework for optimizing the cooling system configuration of chips employing thermoelectric cooling (TEC) elements by extending the theory of inverse-positive matrices and the eigenvalue/eigenvector theory in linear algebra. In this brief, we present a new theorem and its formal proof, which is the key enabler to achieving a provably optimal solution for configuring bias current levels of TEC devices.

Theory and Analysis for Optimization of On-Chip Thermoelectric Cooling Systems

Many advances in Complementary Metal Oxide Semiconductor (CMOS) technology (deep sub micron feature scales, GHz frequencies, and Silicon On Insulator (SOI)fabrication) have been made possible by increases in the packaging density of electronics. These advances began with the introduction of very large scale integration (VLSI). The combination of increased power dissipation and packaging density led to substantial growth in the chip and system heat fluxes, as well as the amplified complexity in electrical signal integrity and mechanical stackup design in the recent years, particularly in high-end computers. With the trend towards miniaturization, heat removal has become a major bottleneck in product development, especially, in low profile systems, telecom servers and blades. According to ITRS roadmap, power dissipation of high performance single chip packages is predicted to be in 218-288 W range, posing a serious challenge with no proven air-cooled solutions to exist.

http://ieeexplore.ieee.org/iel5/9211/29212/01318356.pdf

Thermal and electro-mechanical challenges in design and operation of high heat flux processors

Recent research efforts have been devoted to developing technologies for fabricating electronic circuits in three dimensions using ink-jet processes. The management of generated heat in such circuits will require them to incorporate specialized design features for promoting the removal of unwanted heat from key areas and the limiting of component temperatures to safe levels. Hence, effective tools for predicting the heat transfer characteristics of three-dimensional circuits are required to develop optimum designs.This research encompasses a course of investigation including the development of such design tools and their verification using experimental methods. These experimental methods consisted of thermal tests conducted with prototype circuits constructed in three dimensions, with materials appropriate to the overarching design concept. After the verification process, the investigation proceeded with the construction of numerical models to compare a range of design features expected to enhance passive heat rejection in the discrete resistive component. The relative impact of each of these structures as well as the impact of specific material choices is comparatively evaluated using the developed tools.Further research centered on the fabrication and testing of a circuit which more fully incorporated the 3-D architecture by employing a surface-mount technology (SMT) resistor and by embedding the resistor and conductive components within a cast polymer matrix. Experiments with this circuit and corresponding finite-element models showed that for the power dissipation levels investigated, the presence of the embedding medium actually results in lower temperatures at the resistive component.It was shown in the course of this latter investigation that film coefficients calculated by standard methods do not effectively account for interactions between adjacent convective surfaces in these circuit architectures. A numerical model featuring thermal/fluid dynamics capability and simplified geometry compared to the actual circuit was shown to correlate well with live tests. These model results can be used to calculate improved values for the film coefficients to be applied to models not featuring fluid capability. The models with improved film coefficients similarly provided resistor temperature values which correlated well with the live test results.

Conductive Trace Design in 3-D Circuit Architectures: Heat Transfer Analysis and Experiments

There is a strong need to improve our current capabilities in thermal management and electronic cooling, since estimates indicate that IC power density level could reach 50 W/cm in the near future. This paper presents an innovative approach for thermal modeling of active cooling schemes. It is shown that the principles of energy conversion can be used to overcome the problems of thermal resistance narrowing. Cooling schemes such as mesoscale vapor compression refrigeration, liquid cooling, thermoelectric microcoolers and microchannel heatsinks are discussed and compared relative to heat dissipation potential.

P. Sabounchi

Papers

Lumped capacity thermal circuit diagram of active chip cooling schemes