To achieve a high performance of a system on chip design we should focus on a faster chip communication architecture based on different arbitration scheme. Where all master requests are having different priority. So designing the arbiter having ability to perform in worst corner cases. This paper is introduction to a modified dynamic bus arbiter based on fuzzy logic for a system on chip design architecture. We are considering the worst case here that all masters are requesting for grant to access the bus, so arbiter need to manages the situation based on information about priority scheme, previously granted master and existing lottery arbitration scheme and fuzzy logic arbitration scheme. So we proposed a new two stage technique for granting the access of data bus by creating a subset of various master on the basis of their priority and using dynamic lottery scheme at first stage and fuzzy logic in the second stage in system. This is process by Acceptance rate calculator to decide which algorithm to resolve the grant issue. A hybrid arbiter which results in removing bus starvation and contention problem. This method is also address the pseudo random number is greater than the total partial sum in modified dynamic arbiter based on lottery manager so for this deciding factor is priority selection method and information about the previously granted master which also help to improve the latency. Also making the physical implementation for the design which give the problems related physical implementation of design which affects the frequency of the design. As current design is operated on the frequency 1.2 GHz, as latest CPU are operating on the frequency of 1.8 GHz.

A Hybrid arbiter to accelerate performance of high speed soc

An efficient approach to recognize alphanumeric characters from different type of images using hybrid algorithm has been used in this paper This algorithm can recognize characters from 90 percent blurred image whose blurredness has removed by using convolution operation The algorithm is implemented using vision and motion toolkit of LabVIEW software The real time images of license plates whose information got distorted under different environmental conditions and blurred images are employed for various processing operations eg image enhancement, filtering, segmentation This algorithm has been tested on the license plates of various cars to isolate and identify the characters The performance of algorithm has shown accurate results

Hybrid algorithm for alphanumeric character recognition for vehicles using LabVIEW

In a typical SoC, communication between the sub-blocks is very crucial which dictates the entire SoC performance. As many of the resources are shared in a SoC, the protocol used for communication should have some characteristics which would help in increasing the overall performance of the SoC. AMBA (Advanced Microcontroller Bus Architecture) is one such protocol which characterizes the specifications of the communication bus. The special feature of the bus is that the design, implementation and testing of the sub-blocks in a SoC using AMBA is technology independent. In this paper, a novel bus controller for AMBA is implemented by employing two methodologies namely, Data Flipping and Instruction Decoding. Modelsim from Mentor Graphics and NC launch from Cadence are used for functional simulation. Genus from Cadence is used for synthesis at 180nm. Area, power and timing reports are analyzed after synthesis.

A Novel Bus Controller For Advanced Microcontroller Bus Architecture

A new star detection approach for a satellite-onboard star tracker

ARM introduced the Advanced Microcontroller Bus Architecture (AMBA) 4.0 specifications which includes Advanced eXtensiable Interface (AXI) 4.0. AMBA bus protocol has become the de facto standard SoC bus. That means more and more existing IPs must be able to communicate with AMBA4.0 bus. Based on AMBA 4.0 bus, we designed an Intellectual Property (IP) core of Advanced Peripheral Bus (APB) Bridge, which translates the AXI4.0-lite transactions into APB 4.0 transactions. The bridge provides an interfaces between the high-performance AXI bus and low-power APB domain.

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P. Sharmila Rani

Papers

Design and Implementation Based On Amba4.0 Of Apb Bridge