VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

It is a well-known phenomenon that test power consumption may exceed that of functional operation. ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test. Methods exist to reduce power without dramatically increasing pattern volume for a given coverage. We present case study information on ATPG- and DFT-based solutions for test power reduction.

Minimizing power consumption in scan testing: pattern generation and DFT techniques

When the response to a test vector is captured by state elements in scan based tests, the switching activity of the circuit may be large resulting in abnormal power dissipation and supply current demand High supply current may cause excessive supply voltage droops leading to larger gate delays which may cause good chips to fail tests This paper presents a scalable approach called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. 

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.

System-on-Chip Test Architectures: Nanometer Design for Testability

At-speed test has become a requirement in IC tech- nologies below 180 nm. Unfortunately, test mode switching activity and IR-drop present special chal- lenges to the successful application of structural at- speed tests. In this paper we characterize these prob- lems on commercial ASICs in order to understand how to implement more effective solutions. consumption. Depending on such parameters as gate count, DFT strategies, package type, and other fac- tors, the impact of this problem can range from non- existent to severe. In this paper, we discuss the prac- tical issues associated with power consumption during at-speed tests. We begin by delineating in more detail the nature of power-related phenomena encountered in structured speed tests. We talk about various de- sign features that can be applied to somewhat miti- gate test mode power dissipation. In Section 2, we give a more precise definition of the IR-drop problem which is the focus of this pa- per. We compare IR-drop in slow speed and at-speed structural tests, and also compare it with functional IR-drop. We narrow the focus further to the topic of toggle activity or "switching density" during struc- tured at-speed tests. In Section 3.4 we describe the notion of "quiet" patterns and how they are gener- ated. We follow up with a report of the results we have obtained in experimentation on industrial ASIC designs. Finally we give our suggestions for future work in this area and conclude the paper.

P. Sreeprakash

Papers

A case study of ir-drop in structured at-speed testing