A device for performing single precision floating point arithmetic. The device includes a shared operand generator that receives an operand and outputs a result that is a fixed function of the operand. It also includes an arithmetic circuit comprising a plurality of multiply circuits that calculate partial products of a first and second operand and the result of the shared operand generator. It also includes circuitry to calculate the sum of the partial products and a third operand to produce the arithmetic result.

Single precision array processor

The computation of a minimum and sufficient set of addresses, along with corresponding bit-reversed addresses, is necessary to do unscrambling in conventional FFT (fast Fourier transform) procedures. A matrix-based interpretation of this problem is presented, and typical software and hardware solutions are described. An overall relationship between the two sets of primary and secondary indices is shown, obviating any additional relationship at individual pairwise level. Although the algorithms have been discussed on radix-2 basis, they can be modified for a radix if necessary. >

Bit reversal in FFT from matrix viewpoint

TIlls thesis documents the design details. development. and field testing of an advanced power system hannonic monitor. It begins by reviewing present hannonic standards and hannonic monitoring equipment. It then goes on to describe the design and field use of the first generation hannonic monitor. From the field use a number of problems with this monitor are identified leading to the second generation hannonic monitor known as CHART II. The acronym CHARI' means Continuous Hannonic Analysis in Real-Time. The design of the monitor including the data acquisition and computer processing equipment. as well as the display system. is such that it can acquire multiple channels of power system signals from remote locations. It can compute the hannonics of these signal~; continuously. on a cycle-by-cycle basis. and store only the hannonics of interest. Hannonic computation is perfonned in real-time. with results displayed as they occur. Acquired data can be accurately time stamped for comparison with data from other monitoring sites. enabling simultaneous measurement at remote locations. The key areas of teclmology involved in implementing such an instrumentation system are: data acquisition from power system equipment. digital fibre optics. real-time digital signal processing. high speed m ul ti processing bus systems. real-ti me flulti tasking operating systems. global posi ti oning satellite systems. and computer networking. The application of digital signal processing to power system hannonic measurement is covered. and a field trial with the CHART II monitor is documented.

Power system harmonic monitoring

VLIW Processor Architectures and Algorithm Mappings for DSP Applications

In this paper we describe a novel approach to the scheduling and instruction selection phases of code generation. Our approach mimics that used by human programmers and combines heuristic search with hierarchical planning and a modified means-ends analysis. Optimal code generation is known to be NP-Complete hard. Our algorithm can be executed in time polynomial to the size of the input program and exponential only to the depth of the search. Empirical results show that very good results can be accomplished with depths as small as 3. The quality of the generated code is comparable (in some cases superior) to that of codes generated by human digital signal processing experts.

Panos Papmichalis

Papers

Implementation of fast Fourier transform algorithms with the TMS32020