This paper presents a power-efficient 10/12 bit 40 kS/s SAR ADC for sensor applications. It supports resolutions of 10 and 12 bit and sample rates from DC up to 40 kS/s to accommodate a variety of sensor applications. A Data-Driven Noise-Reduction method is introduced to selectively enhance the comparator noise performance. In this way, a higher ADC resolution can be achieved with a small increase of the power consumption. A self-oscillating comparator is used to generate the bit-cycling clock internally. In this way, the ADC only requires an external clock at the sample-rate frequency. A segmented capacitive DAC with 250 aF unit elements is applied to save power and to reduce DNL errors at the same time. The implemented prototype in 65 nm CMOS occupies an area of 0.076 mm 2. For the two supported resolutions (10/12 bit), the ADC achieves an ENOB of 9.4 and 10.1 bit while consuming 72 and 97 nW from a 0.6 V supply at 40 kS/s. This leads to power efficiencies of 2.7 and 2.2 fJ/conversion-step for 10 bit and 12 bit resolution, respectively. Furthermore, the leakage power, which is below 0.4 nW, ensures that the efficiency can be maintained down to very low sample rates.

A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step

There is provided an information processing device including a display section configured to display a first object in a virtual three-dimensional space having a depth direction of a display screen, an operation section configured to acquire an operation for moving the first object in at least the depth direction, and a controller configured to move the first object on the display screen in accordance with the acquired operation, to execute, when a region of the first object overlaps a first overlap determination region, a first process to one or both of the first and second objects, and to execute, when the region of the first object overlaps a second overlap determination region, a second process to one or both of the first and second objects. The first overlap determination region may be a region obtained by extending the second overlap determination region in at least the depth direction.

Information processing device, information processing method, and program

-This paper describes an on-die, reconfigurable AES encrypt/decrypt hardware accelerator fabricated in 45 nm CMOS, targeted for content-protection in high-performance microprocessors. 100% round computation in native GF(24)2 composite-field arithmetic, unified reconfigurable datapath for encrypt/decrypt, optimized ground & composite-field polynomials, integrated affine/bypass multiplexer circuits, fused Mix/InvMixColumn circuits and a folded ShiftRow datapath enable peak 2.2 Tbps/Watt AES-128 energy efficiency with a dense 2-round layout occupying 0.052 mm2, while achieving: (i) 53/44/38 Gbps AES-128/192/256 performance, 125 mW, measured at 1.1 V, 50 °C, (ii) scalable AES-128 performance up to 66 Gbps, measured at 1.35 V, 50 °C, (iii) wide operating supply voltage range with robust subthreshold voltage performance of 800 Mbps, 409 μW, measured at 320 mV, 50 °C (iv) 37% Sbox delay reduction and 25% area reduction with a compact Sbox layout occupying 759 μm2 (v) 67% reduction in worst-case interconnect length and 33% reduction in ShiftRow wiring tracks and (vi) 43 % reduction in Mix/InvMixColumn area with no performance penalty.

53 Gbps Native ${\rm GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors

Provided is a recording medium in which extents for a base-view and a dependent-view are arranged alternately. The lower limit of the size of the base-view extents is the larger of a first lower limit value and a second lower limit value. The lower limit of the size of the dependent-view extent is a third lower limit value. The first lower limit value is determined so that, in monoscopic video playback, buffer underflow does not occur during jump periods between base-view extents. The second lower limit value is determined so that, in stereoscopic video playback, buffer underflow does not occur during read periods from each base-view extent to a next dependent-view extent. The third lower limit value is determined so that, in stereoscopic video playback, buffer underflow does not occur during read periods from each dependent-view extent to the next base-view extent.

Recording medium, reproduction device, and integrated circuit

The increased resolution of Quad Full High Definition (QFHD) offers significantly enhanced visual experience. However, the corresponding huge data throughput of up to 530 Mpixels/s greatly challenges the design of real-time video decoder VLSI with the extensive requirement on both DRAM bandwidth and computational power. In this work, a lossless frame recompression technique and a partial MB reordering scheme are proposed to save the DRAM access of a QFHD video decoder chip. Besides, pipelining and parallelization techniques such as NAL/slice-parallel entropy decoding are implemented to efficiently enhance its computational power. The chip supporting H.264/AVC high profile is fabricated in 90 nm CMOS and verified. It delivers a maximum throughput of 4096×2160@60fps, which is at least 4.3 times higher than the state-of-the-art. DRAM bandwidth requirement is reduced by typically 51%, which fits the design into a 64-bit LPDDR SDRAM interface and results in 58% DRAM power saving. Meanwhile, the core energy is saved by 54% by pipelining and parallelization.

A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip

Recently reported continuous-time (CT) ΔΣ modulators with opamp bandwidth compensation and high-order single-opamp integrators have achieved FoM values well below 100fJ/conv-step [1-3]. With loop-filter power greatly reduced, power dissipation in multibit quantizers becomes especially significant. For example, the quantizer in [2] accounts for 2.8mW of 8.5mW total power dissipation. Also, the input capacitance of multibit quantizers and the output parasitics of excess loop delay (ELD) compensation DACs result in increased power demand for summing circuits. To minimize power dissipation, two recent works use 1b quantizers with FIR DACs and replace ELD compensation DACs with a DAC followed by analog filter [3] or with feedback to the pre-amplifier [4]. ELD compensation may also be realized using digital logic following the quantizer [5]. This paper presents a low-power solution based on a highly digital multibit quantizer with embedded feedback to compensate for finite opamp bandwidth along with ELD. The quantizer consumes less than 10% of the total power and simplifies the analog circuits into a single DAC plus a feedforward loop filter with relaxed opamp requirements. Digital correction at the modulator output suggested by early work [6] is employed to shape DAC mismatch with the inherent noise transfer function (NTF) and to further relax circuit constraints. These digitally assisted techniques enable a CT ΔΣ modulator to achieve an FoM below 28fJ/conv-step.

A 28fJ/conv-step CT ΔΣ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer

A Blu-ray Disc (BD) player, back-end SoC supporting multiple protection, video and display formats is fabricated in a 90nm 1P7M CMOS process with a core area of 62.95mm2. This SoC adopts a general copy protection (GCP) unit to integrate various kinds of protection algorithms (e.g. AES, CSS, CPPM/CPRM, DES, SHA-1/MD5), designs a dedicated memory management unit (MMU) for realizing multiple video standards (e.g. MPEG-1/2/4, H.264, VC-1), and exploits a reduced display path so as to provide two display outputs simultaneously. Moreover, a 3.7Gb/s/ch HDMI TX circuit is proposed to support different color depths and display resolutions. For BD player applications, AACS decryption, 60fps H.264 decode, 1080pHD with 480pSD picture overlay (PIP), and HDMI-1.3 12b deep color-mode output is achieved at 200MHz, 200MHz, 148.5MHz and 222.5MHz clock frequency, respectively. It dissipates about 1.605W at 1.0V core and 1.2/3.3V HDMI macro. The chip features are summarized in Fig. 8.4.1.

A multi-format Blu-ray player SoC in 90nm CMOS

A low-power and high-dynamic-range downlink ADC is the most critical building block in a cellular receiver design. A continuous-time delta-sigma modulator (CTDSM), which gets the benefit of inherent anti-alias filtering, is a common architecture choice for the ADC. However, low power dissipation dictates a low over-sampling ratio (OSR) since the bandwidth of the loop filter, DAC switching rate, and the clock frequency of the subsequent digital front-end are all proportional to the sampling frequency. Due to the desire for low OSR, a higher quantization level is required to maintain dynamic range, and the successive approximation register (SAR) quantizer, which gets the benefits of power and area efficiency compared to a flash quantizer, becomes more attractive in nanometer processes. However, the issue with a SAR quantizer in a high-speed CTDSM is the limited signal processing time available to achieve lower quantization noise and feedback DAC linearization. In this work, a 12 cycle, 400MHz passive noise-shaping SAR (NS-SAR) is embedded in a low-OSR CTDSM to fulfill the link budget requirement. Two techniques to satisfy the requirement of shorter signal processing time to DAC feedback path are introduced: segmented mismatch error shaping (S-MES) to achieve linear segmented DACs and digital noise coupling compensation filtering (DNCCF) to achieve low quantization noise.

20.4 An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS

A 39MHz bandwidth (BW) CTSDM ADC realized by aggregating two 19MHz BW CTSDM ADCs with a noise-injected technique is presented. The in-band noise is improved by 4.77dB by this technique. The ADC samples at 832MS/s, achieves 72dB DR in 39MHz BW and 78dB DR in 19MHz BW. This aggregated ADC is implemented in 16-nm FinFet technology with 0.23 mm2 active area and 6.2 mW per ADC, and thereby achieves FoM DR of 167.1dB in 39MHz BW, and FoM DR of 173.4dB in 19MHz BW.

A 16nm FinFet 19/39MHz 78/72dB DR noise-injected aggregated CTSDM ADC for configurable LTE advanced CCA/NCCA Application

A fully dynamic flash ADC is attractive for its low-power and low-input capacitance natures. It has minimal static current consumption, and its power and area costs diminish as process advances. However, the comparators thresholds, which are set by the built-in offsets, are sensitive to supply and temperature drifts. This threshold variation may result in up to ±20% ADC gain error with ENOB degradation. This paper presents a calibration scheme used to restore the ADC performance without interrupting the normal operation. This technique enables the practical use of fully dynamic flash ADCs and is demonstrated in the quantizer design of a continuous-time ΔΣ modulator. The quantizer accounts for 0.3mW of 3.74mW total power dissipation and relaxes the opamp requirements. The modulator achieves 75.6dB SNDR and 82dB DR over a 10MHz BW, leading to an Walden FoM of 38fJ/conv-step.

Pao-Cheng Chiu

Papers

A 28fJ/conv-step CT ΔΣ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer

A multi-format Blu-ray player SoC in 90nm CMOS

20.4 An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS

A 16nm FinFet 19/39MHz 78/72dB DR noise-injected aggregated CTSDM ADC for configurable LTE advanced CCA/NCCA Application

A background calibration technique for fully dynamic flash ADCs