An apparatus that allows for separating and collecting a fraction of a sample. The apparatus, when used with a centrifuge, allows for the creation of at various fractions in the apparatus. A buoy system that may include a first buoy portion and a second buoy member operably interconnected may be used to form at least three fractions from a sample during a substantially single centrifugation process. Therefore, the separation of various fractions may be substantially quick and efficient. Also selected fractions from the sample can be applied to a patient, either alone or as part of a mixture.

Apparatus and Method for Separating and Concentrating Fluids Containing Multiple Components

A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls are rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (Leff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom. Because of the V-shaped structure of the gate, the effective saturated length of the channel with drain voltage applied only extends from the edge of the source to just prior to the tip of the V-shaped structure in the interior of the semiconductor substrate. The drain side of the V-shaped structure becomes a depletion region due to the applied drain voltage. Due to this characteristic of such a structure, the surface width of the gate can be, for example, two or more times the distance of the desired channel length thereby permitting conventional lithography to be used to define the gate lengths much shorter than the lithographic limit.

Short channel self-aligned VMOS field effect transistor

A method of making an electrically-programmable memory array in which the memory elements are capacitor devices formed in anisotropically etched V-grooves, providing enhanced dielectric breakdown at the apex of the groove. After breakdown, a memory element exhibits a low resistance to a grounded substrate. The method includes forming access transistors in series with the memory elements, and polycrystalline silicon, deposited to form control gates of the access transistors, also forms address lines. Oxide is formed in the V-groove thinner than the gate oxide thickness formed for the access transistor, providing a lower programming voltage. These factors provide a very small, high speed device.

Method of making high density VMOS electrically-programmable ROM

A polycrystalline silicon film which is to be a channel is in a trench provided in a main surface of a silicon substrate. A gate insulating film is on the periphery of a polycrystalline silicon film. A gate electrode is on the periphery of the gate insulating film. A silicon oxide film is on the periphery of the gate electrode. A source/drain film is on the periphery of the silicon oxide film. A silicon oxide film is on the periphery of the source/drain film. A source/drain film is electrically connected to the polycrystalline silicon film. A source/drain film is electrically connected to the polycrystalline silicon film. Since the polycrystalline silicon film extends along the depth direction of trench, a channel length can be sufficient to prevent a short channel effect. Also, compared to the case in which an epitaxial layer is used as a channel, since the polycrystalline silicon film is used as a channel, the time required for manufacturing the device can be shortened.

Vertical field effect transistor with a trench structure

A semiconductor integrated circuit comprising semiconductor regions in the form of first and second protruding poles that are provided on a semiconductor layer formed on a semiconductor substrate or an insulating substrate, and that are opposed to each other with an insulating region sandwiched therebetween, a p-channel FET provided in the first semiconductor region, and an n-channel FET provided in the second semiconductor region. These FET's have source and drain regions on the upper and bottom portions of the semiconductor regions, and have gate electrodes on the sides of the semiconductor regions. The insulation region between the protruding pole-like semiconductor regions is further utilized as the gate electrode and the gate insulating film.

Complementary MOS integrated circuits having vertical channel FETs

An improved short-channel complementary MOS transistor structure is provided. The problems of low punch-through voltage breakdown, and "short-channel effects" are particularly addressed and solved. Accurate and precise field protection of all area surrounding the channel, source and drain regions of both the p-channel MOS transistor device and the n-channel transistor device is simply and effectively accomplished. The threshold voltage of the n-channel MOS transistor device is precisely controlled by a boron implantation. The method of manufacturing such device is disclosed.

Short-channel V-groove complementary MOS device

An Array Matrix of red and infrared light emitting diodes (LED) are mounted onto to a flexible printed circuit board (FPCB) to produce a compact and wearable Low Level Light Therapy (LLLT) Device. An effective heat releasing method is employed to enable a long period of continuous use of the LLLT device.

Paul H. Ouyang

Papers

Short-channel V-groove complementary MOS device

System and method for treating ailments with light