A mesh connected local area network provides automatic packet switching and routing between host computers coupled to the network. The network has a multiplicity of cut-through, nonblocking switches, each capable of simultaneously routing a multiplicity of data packets. Low host-to-host latency is achieved through the use of cut-through switches with separate internal buffers for each packet being routed. The switches are interconnected with one another and are coupled to the host computers of the network by point to point full duplex links. While each switch can be coupled to ten or more network members, i.e., switches and hosts, each link is coupled to only two network members and is dedicated to carrying signals therebetween. Whenever a new switch or link is added to the network, and whenever a switch or link fails, the switches in the network automatically reconfigure the network by recomputing the set of legal paths through the network.

High-speed mesh connected local area network

A method and system for routing information packets among nodes interconnected by links to form a network, each information packet traversing a path of links and nodes from a source node to a destination node. Information indicating the relationships of nodes and links in the network is assembled in the source node. The entire route from the source node to the destination node is computed prior to sending each information packet and the information packet is routed through the network in accordance with the computed route. Information is assembled about the local topology of the network including the identities of the neighboring nodes which are connected via links to the local node. The local topology information of each local node is distributed to every other node in the network. Each node is assigned a unique identifier, a unique public key and an associated private key. The source node's assigned identifier, public key and private key are assembled in the source node along with the assigned identifier, public key and associated private key of each of a plurality of other nodes. The computed route is enclosed in a packet. The packet containing the routes is signed and transmitted to each node on the route.

Robust packet routing over a distributed network containing malicious failures

Apparatus, and accompanying methods for use therein, for a large (e.g. approximately 1 Terabit/second), fault tolerant packet switch (200), particularly suited for asynchronous mode transfer (ATM) communication, which utilizes cell address look-ahead in conjunction with parallel planes of self-routing cross-points (550), staggered time phased contention resolution and shared memory based input and output modules (260 and 270, respectively). Each incoming packet cell has added thereto an additional header field containing information identifying a particular output module and a particular output port of that module. An input module associated with the switching crosspoints changes the additional header information to identify the particular output module of the next subsequent packet cell.

Packet address look-ahead technique for use in implementing a high speed packet switch

In a fast packet switching system, packet distributers are associated respectively with input ports for receiving successive packets therefrom and attaching a timeslot number to each of the received packets, and uniformly distributing the packets to output terminals of each distributer. Packet switches are provided corresponding in number to the output terminals of each packet distributer. Each packet switch has input terminals corresponding in number to the packet distributers and output terminals corresponding in number to the output ports. The input terminals of each packet switch are coupled to respective output terminals of the distributers for switching a packet from one of its input terminals to one of its output terminals in accordance with a destination address contained in the packet. Packet sequencers are associated respectively with the output ports. Each packet sequencer has input terminals coupled to respective output terminals of the packet switches for examining the timeslot numbers attached to packets from its input terminals and delivering the packets to the associated output port in accordance with the examined timeslot numbers.

Switching system with time-stamped packet distribution input stage and packet sequencing output stage

An ATM telecommunications switch includes a plurality of parallel data switching planes and a parallel control plane, each plane having an equal number of input ports and output ports and a central switching unit to switch each input port to any output port. A single data stream is divided between a plurality of input ports and the data is concatenated from a plurality of output ports to reconstitute the data stream. A first rotator connects each input port cyclically to each timelslot of the central switching unit and a second rotator connects each timeslot of the central switching unit cyclically to each output port.

ATM switching arrangement

A packet switching architecture in which switching network nodes automatically determine nonblocking paths through a switching network in response to address information. The switching network comprises stages of broadcast and routing nodes. The broadcast nodes are responsive to the transmission of address information from an input port to create a plurality of paths through the switching network and to communicate on this plurality of paths the address information to the routing stages. Each of the routing switch nodes is responsive to receipt of address information to select one of the paths to an address-designated output port. The final path is established by the output port transmitting an acknowledge signal back through the switching network. Each node upon receipt of the acknowledge signal establishes the path through the itself.

Nonblocking self-routing packet and circuit switching network

A switching system having a control network for establishment of a path and a data switching network responsive to the path determined by the control network for switching data between a plurality of input ports to a plurality of output ports. The control network is a self-routing network that is fabricated utilizing electronic devices; whereas, the data switching network is fabricated using photonic devices. The electronic network is of the butterfly architecture and the photonic network is of the cross-bar architecture. A translation circuit is utilized to convert the path determined through the self-routing butterfly control network for use in determining the path through the photonic cross-bar network.

Payne William Andrew

Papers

Nonblocking self-routing packet and circuit switching network

Switching system having multiple parallel switching networks

Non-blocking self-routing exchange network