Showing papers by "Per Stenström published in 1993"

An adaptive cache coherence protocol optimized for migratory sharing

Abstract: Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a write-invalidate protocol result in invalidation actions that could be eliminated. For this type of sharing, called migratory sharing, each processor typically causes a cache miss followed by an invalidation request which could be merged with the preceding cache-miss request.In this paper we propose an adaptive protocol that invokes this optimization dynamically for migratory blocks. For other blocks, the protocol works as an ordinary write-invalidate protocol. We show that the protocol is a simple extension to a write-invalidate protocol.Based on a program-driven simulation model of an architecture similar to the Stanford DASH, and a set of four benchmarks, we evaluate the potential performance improvements of the protocol. We find that it effectively eliminates most single invalidations which improves the performance by reducing the shared access penalty and the network traffic.

Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors

Abstract: To offset the effect of read miss penalties on processor utilization in shared-memory multiprocessors, several software- and hardware-based data prefetching schemes have been proposed. A major advantage of hardware tech niques is that they need no support from the programmer or compiler. Sequential prefetching is a simple hardware-controlled prefetching technique which relies on the automatic prefetch of consecutive blocks following the block that misses in the cache. In its simplest form, the number of prefetched blocks on each miss is fixed throughout the exe cution. However, since the prefetching efficiency varies during the execution of a program, we propose to adapt the number of pref etched blocks according to a dynamic measure of prefetching effectiveness. Simulations of this adaptive scheme show significant reductions of the read penalty and of the overall execution time.

The detection and elimination of useless misses in multiprocessors

Abstract: In this paper we introduce a new classification of misses in shared-memory multiprocessors based on interprocessor communication. We identify the set of essential misses, i.e., the smallest set of misses necessary for correct execution. Essential misses include cold misses and true sharing misses. All other misses are useless misses and can be ignored without affecting the correctness of program execution. Based on the new classification we compare the effectiveness of five different protocols which delay and combine invalidations leading to useless misses. In cache-based systems the protocols are very effective and have miss rates close to the essential miss rate. In virtual shared memory systems the techniques are also effective but leave room for improvements.

The Cachemire Test Bench A Flexible And Effective Approach For Simulation Of Multiprocessors

Abstract: The CacheMire Test Bench – A Flexible and Effective Approach for Simulation of Multiprocessors

Performance evaluation of link-based cache coherence schemes

Abstract: The authors have evaluated the implementation and performance tradeoffs between three directory-based cache coherence protocols. They study two link-based approaches, called tree-based and linear-list protocols, and contrast their performance and implementation cost with that of a full-map protocol. Using program-driven simulation and a set of three benchmark programs, it was found that tree-based and linear-list protocols performed almost as well as full-map protocols but with a considerably lower implementation cost. However, if the sharing set is large, linear-list schemes may suffer because of the large write latency while tree-based protocols still perform well. >

1993 International Conference on Parallel Processing Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors

Abstract: To offset the effect of read miss penalties on processor utilization in shared-memory multiprocessors, several software- and hardware-based data prefetching schemes have been proposed. A major advantage of hardware tech¬ niques is that they need no support from the programmer or compiler. Sequential prefetching is a simple hardware-controlled prefetching technique which relies on the automatic prefetch of consecutive blocks following the block that misses in the cache. In its simplest form, the number of prefetched blocks on each miss is fixed throughout the exe¬ cution. However, since the prefetching efficiency varies during the execution of a program, we propose to adapt the number of pref etched blocks according to a dynamic measure of prefetching effectiveness. Simulations of this adaptive scheme show significant reductions of the read penalty and of the overall execution time.

Using Graphics and Animation to Visulize Instruction Pipelining and its Hazards

Abstract: The breakthrough of pipelined microprocessors has brought about a need to teach instruction pipelining in electrical and computer engineering curricula at the undergraduate level to a considerable depth. Although the idea of pipelining is conceptually simple, students often find pipelining difficult to visualize. Only the most talented students assimilate the ideas of how hazard issues are eliminated. Based on the pedagogical approach used in the landmark book “Computer Architecture—A Quantitative Approach” by John Hennessy and David Patterson, we have developed a graphical tool that uses animation and other graphical techniques to visualize how a pipelined datapath and control unit work. In this paper, we describe the graphical tool and outline a laboratory that makes use of it.

Visualisation of Cache Coherence Bottlenecks in Shared Memory Multiprocessor Applications

Abstract: Shared memory multiprocessors are becoming more and more important but one major problem is how to keep the processor caches coherent. Many diff erent solutions to this problem exist and the performance of a given program depends largely on the access pattern observed to shared data, the sharing behaviour. We discuss in this paper how to characterise and visualise sharing behaviour. In terms of cache coherence the degree of sharing, the access mode and the temporal granularity are found to be essential in order to describe and understand sharing behaviour. The sharing behaviour can be measured by simulation and visualised in asharing profile diagram. We use an unblocked matrix multiplication and two diff erent ways of parallelising a blocked matrix multipl ication algorithm to illustrate the problems involved and how the sharing profil e can aid in choosing the right algorithm.