An organic light emitting display apparatus that has high (or improved) contrast and/or impact resistance. The organic light emitting display apparatus includes: a substrate; an organic light emitting device on the substrate to display an image; a sealing member on the organic light emitting device; a semitransparent film on a surface of the sealing member facing away from the organic light emitting device to transmit a portion of external light and to reflect another portion of the external light; a passivation film on the semitransparent film to protect the semitransparent film; and a transmissive black layer between the sealing member and the organic light emitting device to increase contrast, wherein the semitransparent film has a refractive index greater than that of the passivation film.

Organic light emitting display apparatus

A system and method for calibrating light output from an LED is provided. The system includes a support on which an LED is positioned, a photosensor to measure the light output from the LED, and means for calibrating and adjusting the light output of the LED. Calibration is accomplished by measuring the light output from the LED, comparing such output against a reference value, and adjusting the measured output against the reference value.

Systems and methods for calibrating light output by light-emitting diodes

A smart memory (10) is provided that includes data storage (12 and 18) and a processing core (14 and 16) for executing instructions stored in the data storage area (12 and 18). Externally, smart memory (10) is directly accessible as a standard memory device. In a first mode of operation, the smart memory (10) is a data storage facility for an associated central processing unit (22). In a second mode of operation, the smart memory (10) is a storage facility for the processing core (14 and 16) and for central processing unit (22) for simultaneous execution of instructions. The central processing unit (22) controls the mode of operation and determines the instructions executed by the processing core (14 and 16). The wide data bus, available with an integrated processor/storage facility, permits certain processing operations to be off-loaded to the smart memory (10) where the processing operations can be performed more efficiently.

Apparatus and method for a memory unit with a processor integrated therein

A resynchronization circuit for processing a stream of data values read from a memory system, and a method of operating the same. The resynchronization circuit includes a first in, first out (FIFO) memory device, a phase locked loop circuit and a latency control circuit. The FIFO memory device receives a stream of data values and a first clock signal from the memory system. The data values are sequentially read into the FIFO memory device in response to the first clock signal. The phase locked loop circuit receives a second clock signal, and in response generates an output clock signal which leads in phase the second clock signal. The output clock signal is provided to the FIFO memory device to cause the data values to be sequentially read from the FIFO memory device. As a result, a stream of data values is generated which is synchronized with the second clock signal. The latency control circuit, which is coupled to the FIFO memory device, enables the data values to be read from the FIFO memory device after a selectable delay period which follows the initiation of the read operation from the memory system.

Resynchronization circuit for a memory system and method of operating same

Improved circuitry for connecting the memory array to a data bus allows for high speed accessing of the memory array. Sense amplifier latches are coupled to each column of memory cells. The latched sense amplifiers are coupled to decoders which, in turn, are coupled to data amplifiers. The data amplifiers are coupled to a data bus. Data being read from or written to the memory cells is via the sense amplifier latches, the decoders, and data amplifiers.

Memory array with read/write methods

A single-chip microcomputer comprises a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), four I/O ports (11-14) and various power supply, clock, and control inputs One of the I/O ports (13) is user programmable by application of specific signals to mode selection pins (P20-22) for configuration in several possible ways The programmable port comprises a plurality of lines which each may be individually programmed as input or output lines to peripheral equipment associated with the microcomputer Alternatively, the port lines can be programmed to serve as a bidirectional data bus to external memory Alternatively, the port lines can be programmed to be multiplexed data and address lines to external memory Bus arbitration logic is provided to route data to the CPU from either on-chip memory or external memory

Microcomputer with programmable multi-function port

A universal bus interface circuit can be used in conjunction with either synchronous or asynchronous bus systems. An input terminal is monitored to determine if the bus is synchronous or asynchronous. If the bus is asynchronous, a synchronization circuit generates a synchronous control signal for internal use from an asynchronous select signal. The synchronization circuit also generates an asynchronous hand-shake or acknowledge signal which is applied to the input terminal to indicate completion of the operation. The input terminal is monitored by a host processor.

Universal interface circuit for synchronous and asynchronous buses

A RAM being powered by a standby voltage supply and having control circuitry to save all or a portion of the information stored in the RAM during power up and power down is provided. A latch is used to hold an input signal just prior to power down to just after power up. The latch is coupled to read and write and word select logic so that the latch can inhibit the read and write logic as well as inhibiting the addressability of any storage cells in the retained portion of the RAM during power up and power down. Transistors having a control electrode are connected to the word select lines of the RAM and hold the word select lines near zero voltage during power up and power down to prevent information from flowing on the word select lines. The control electrodes of the transistors are connected to an output of the latch.

Ram retention during power up and power down

There is provided a voltage level detecting circuit useful as power-up/power-down voltage indicator for a field effect transistor integrated circuit. A constant voltage reference generator is provided by a depletion type transistor in series with two enhancement type transistors coupled between power supply terminals of the integrated circuit chip. Each of the enhancement type transistors have their gate electrodes connected to their drain electrodes while the depletion type transistor has its gate electrode connected to the more negative or reference terminal of the power supply voltage. A constant voltage output is taken from between the junction of one of the enhancement mode transistors and the depletion type transistor. This constant voltage output can be compared against a voltage obtained from a voltage divider circuit which provides an output that varies in accordance with variations in the power supply. The voltage level detector circuit is particularly useful in microprocessors and microcomputer integrated circuit chips.

FET Voltage level detecting circuit

A mode selection circuit is disclosed which is suitable for configuring a data processor at the time at which the data processor is initialized with a reset signal. Mode selection latches are coupled to terminals normally used as an input/output port for the data processor and the latches are clocked with a signal generated by a level detector circuit which senses the reset signal. The mode selection latches are programmed by applying appropriate logic levels to the terminals of the input/output port at the time at which the data processor is being reset. The circuitry is adapted for allowing the connection of a diode from a terminal of the input/output port to the reset terminal of the data processor in order to program a low logic level into the corresponding mode detection latch.

Pern Shaw

Papers

Microcomputer with programmable multi-function port

Universal interface circuit for synchronous and asynchronous buses

Ram retention during power up and power down

FET Voltage level detecting circuit

Programmable mode select by reset