Showing papers by "Peter A. Beerel published in 2012"
07 May 2012
TL;DR: Performance bounds for such conditional circuits based on the cycle times of successively larger collections of these underlying modes prove the somewhat intuitive result that treating a conditional circuit as unconditional for slack matching guarantees the circuit performance requirement conservatively.
Abstract: Asynchronous circuits with conditional behavior often have distinct modes of operation each of which can be modeled as a marked graph with its own performance target. This paper derives performance bounds for such conditional circuits based on the cycle times of successively larger collections of these underlying modes. Our bounds prove the somewhat intuitive result that treating a conditional circuit as unconditional for slack matching guarantees the circuit performance requirement conservatively. We also prove the somewhat counter-intuitive result that the average cycle time of a conditional circuit may be worse than the weighted average of the cycle time of its underlying collection of modes. Finally, the paper outlines the potential application of these bounds to future improvements in slack matching of such conditional circuits.
10 citations
04 Sep 2012
TL;DR: It is demonstrated how operand-isolation cells introduced by standard synthesis algorithms can guide the addition of conditional communication primitives to surround blocks of asynchronous logic with conditional communication reducing switching activity and power.
Abstract: In this paper, we model conditional communication primitives of asynchronous circuits as three-valued logic operators and adopt the theory of observability don’t cares to create a theoretical framework that can be used to guide the optimization of conditional communication in asynchronous circuits. In particular, using this framework we demonstrate how operand-isolation cells introduced by standard synthesis algorithms can guide the addition of conditional communication primitives to surround blocks of asynchronous logic with conditional communication reducing switching activity and power. Our experimental results show for a 32-bit ALU, we achieve an average of 53% power reduction for about a 4% increase in area with no impact in performance.
4 citations
30 Sep 2012
TL;DR: This work presents a polynomial complexity flow for transforming a Free-Choice PTnet into a new formalism for Interacting FSMs, i.e Multiple, Synchronised FSMs (MSFSMs), a compact InteractingFSMs model, potentially implementable using any existing monolithic FSM implementation method.
Abstract: FSM and PTnet control models are pertinent in both software and hardware applications as both specification and implementation models. The state-based, monolithic FSM model is directly implementable in software or hardware, but cannot model concurrency without state explosion. Interacting FSM models have so far lacked the formal rigor for expressing the synchronising interactions between different FSMs. The event-based, PTnet model is able to model both concurrency and choice within the same model, however lacks a polynomial time flow to implementation, as current methods of exposing the event state space require a potentially exponential number of states. In this work, we present a polynomial complexity flow for transforming a Free-Choice PTnet into a new formalism for Interacting FSMs, i.e Multiple, Synchronised FSMs (MSFSMs), a compact Interacting FSMs model, potentially implementable using any existing monolithic FSM implementation method. We believe that such a flow can in the long term bridge the event and state-based models. We present execution time and state space results of exercising our flow on 25 large PTnet specifications, describing asynchronous control circuits, and contrast our results to the popular Petrify tool for PTnet state space exploration and circuit implementation. Our results indicate a very significant reduction in both state space size and execution time.
2 citations