An approach to fault-tolerant design is described in which a computing system S and an algorithm A to be executed by S are both defined by graphs whose nodes represent computing facilities. A is executable by S if A is isomorphic to a subgraph of S.A k-fault is the removal of k nodes (facilities) from S.S is a k-fault tolerant (k-FT) realization of A if A can be executed by S with any k-fault present in S. The problem of designing optimal k-FT systems is considered where A is equated to a 0-FT system. Techniques are described for designing optimal k-FT realizations of single-loop systems; these techniques are related to results in Hamiltonian graph theory. The design of optimal k-FT realizations of certain types of tree systems is also examined. The advantages and disadvantages of the graph model are discussed.

A Graph Model for Fault-Tolerant Computing Systems

This paper presents a taxonomy, or naming scheme, for systems of interconnected computers. I t is an attempt to provide an implementation-independent method by which to identify demgns, and a common context in which to discuss them. The taxonomy is based on interprocessor message handling and hardware interconnection topology, and distinguishes ten basic multiple-computer architectures. Various relevant attributes are identified and discussed, and examples of actual designs are given for each architecture.

Computer Interconnection Structures: Taxonomy, Characteristics, and Examples

A bus structure for use in a computer network requiring high availability and reliability of communications. Multiple bus paths (2A, 2B) are provided. When a transmission is to be made, under most circumstances the path is selected at random, with all paths being equally probable. Thus, failure of a path is detected quickly. Each host device in the network connects to the bus paths through an interface, or port (1). The task of path selection is carried out by the ports, independently of the host devices. The ports also detect path failures and automatically switch over to an alternate good path upon detection of such a failure, all without host involvement. Virtual circuit communications between hosts are transparent to path selection and switching, so the only indication to a host device of a path failure is a decrease in throughput. Most of the signal processing apparatus of each port (10, 20A, 20B) is shared by the paths, only one path being supported at any given time. Thus, the addition of a second bus path involves only minimal cost.

Dual path bus structure for computer interconnection

Markovian models are developed for the performance analysis and comparison of several single bus multiprocessor architectures. Processors are assumed to cooperate in a message passing fashion, and messages are exchanged through common memory areas. Four architectures are considered in this paper which differ in the location of the common memory modules. Contention for shared resources is modeled and the corresponding efficiency loss is studied. Numerical results are obtained for the processing power of each architecture, introducing simplifying assumptions that allow a compact Markovian system description.

Comparative Performance Analysis of Single Bus Multiprocessor Architectures

A network or interconnect structure utilizes a data flow technique that is based on timing and positioning of messages communicating through the interconnect structure. Switching control is distributed throughout multiple nodes in the structure so that a supervisory controller providing a global control function and complex logic structures are avoided. The interconnect structure operates as a "deflection" or "hot potato" system in which processing and storage overhead at each node is minimized. Elimination of a global controller and buffering at the nodes greatly reduces the amount of control and logic structures in the interconnect structure, simplifying overall control components and network interconnect components and improving speed performance of message communication.

Multiple level minimum logic network

Busses are vital elements of a digital system---they interconnect registers, functional modules, subsystems, and systems. As technological advances raise system complexity and connectivity, busses are being recognized as primary architectural resources which can frequently be the limiting factor in performance, modularity, and reliability. The traditional view of bussing as just an ad hoc way of hooking things together can no longer be relied upon to produce even viable much less cost-effective solutions to these increasingly sophisticated interconnect problems.

A systematic approach to the design of digital bussing structures

Hypercube architectures

The evolution of finite element programs and program systems for engineering analysis and the more recent pioneering development of expert systems are briefly described.1 From these we proceed to develop some general principles and guidelines using expert systems with finite element techniques and novel computer architectures.

Toward expert systems in finite element analysis

Data structures and computer architecture: Design issues at the hardware/software interface

This paper discusses an application of Denning's working set model to a design problem that arose in the development of an avionics computer. The working set model was used to aid the choice of optimum page size based on actual operating program trace data: from the E-2B aircraft. Extrapolating the E-2B workload until it “saturated” the new design on a working set idealization of the new architecture led to a preferred size for program pages on backing store.

Peter C. Patton

Papers

A systematic approach to the design of digital bussing structures

Hypercube architectures

Toward expert systems in finite element analysis

Data structures and computer architecture: Design issues at the hardware/software interface

Page size selection for a real time computer