This invention generally relates to power semiconductor devices, and in particular to improved thyristor devices and circuits. The techniques we describe are particularly useful for so-called MOS-gated thyristors. We describe a thyristor comprising a plurality of power thyristor devices connected in parallel, each said thyristor device being operable at a device current which the device has an on-resistance with a positive temperature coefficient.

Power Semiconductor Devices

A semiconductor component, which comprises a pn junction, where both the p-conducting and the n-conducting layers of the pn junction constitute doped silicon carbide layers and where the edge of at least one of the conducting layers of the pn junction, exhibits a stepwise or uniformly decreasing total charge or effective surface charge density from the initial value at the defined working junction to a zero or almost zero total charge at the outermost edge of the junction following a radial direction from the central part of the junction towards the outermost edge.

SiC semiconductor device comprising a pn junction with a voltage absorbing edge

A DMOS power transistor has a vertical gate and a planar top surface. A vertical gate fills a rectangular groove lined with a dielectric material which extends downward so that source and body regions lie on each side of the dielectric groove. Carriers flow vertically between source and body regions and the structure has a flat surface for all masking steps.

Method for making planar vertical channel DMOS structures

The present invention and process relates to crystal lattice mismatched semiconductor composite having a first semiconductor layer and a second semiconductor growth layer deposited thereon to form an interface wherein the growth layer can be deposited at thicknesses in excess of the critical thickness, even up to about 10x critical thickness. Such composite has an interface which is substantially free of interface defects. For example, the size of the growth areas in a mismatched In 0 .05 Ga 0 .95 As/(001)GaAs interface was controlled by fabricating 2-μm high pillars of various lateral geometries and lateral dimensions before the epitaxial deposition of 3500Å of In 0 .05 Ga 0 .95 As. The linear dislocation density at the interface was reduced from >5000 dislocations/cm to about zero for 25-μm lateral dimensions and to less than 800 dislocations/cm for lateral dimensions as large as 100 μm. The fabricated pillars control the lateral dimensions of the growth layer and block the glide of misfit dislocations with the resultant decrease in dislocation density.

Method for reducing or eliminating interface defects in mismatched semiconductor epilayers

A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by a snap-back phenomenon. After an MOS gate structure is formed in a front surface of an FZ wafer, a rear surface of the FZ wafer is ground. Then, the ground surface is irradiated with protons and irradiated with two kinds of laser beams different in wavelength simultaneously to thereby form an N + first buffer layer and an N second buffer layer. Then, a P+ collector layer and a collector electrode are formed on the proton-irradiated surface. The distance from a position where the net doping concentration of the N + first buffer layer is locally maximized to the interface between the P+ collector layer and the N second buffer layer is set to be in a range of 5 μm to 30 μm, both inclusively.

Semiconductor device and method of producing the same

Bei einem feldgesteuerten Thyristor mit einer Schichtenfolge aus Anodenschicht (6), Kanalschicht (5) und kathodenseitig abwechselnd angeordneten Gatebereichen (8) und Kathodenbereichen (3) wird eine Verbesserung der Blockierverstarkung durch eine p-Dotierung der Seitenwande der die Kathodenbereiche (3) voneinander trennenden Graben (10), und/oder eine zusatzliche, niedrig p-dotierte Zwischenschicht (9) erreicht, die zwischen benachbarten Gatebereichen (8) angeordnet ist. In a field-controlled thyristor having a sequence of layers of anode layer (6), the channel layer (5) and the cathode side, alternately arranged gate regions (8) and cathode regions (3) is an improvement of the blocking gain by a p-doping of the sidewalls of the cathode regions (3) from each other, separated trenches (10), and / or an additional, low p-doped intermediate layer (9) is reached, which is disposed between adjacent gate regions (8).

Gate turn-off power semiconductor device

Semiconductor devices for power conditioning

In a semiconductor component, a pn junction which emerges at a main surface (2) of a semiconductor substrate (1) at the edge of a highly doped zone (3) is formed by a laterally bounded, highly doped zone (3) extending inwards from a main surface (2) of the semiconductor substrate (1) and by a lightly doped zone surrounding the highly doped zone. The edge of the highly doped zone (3) is formed by a guard zone (6b) whose doping density gradually decreases in a direction parallel to the main surface (2) from the highly doped zone (3) towards the pn junction. Any surface breakdown of the pn junction is prevented by the fact that the guard zone (6b) has a maximum penetration depth near the highly doped zone (3) and that the maximum penetration depth of the guard zone (6b) is greater than the penetration depth of the adjacent highly doped zone (3). The guard zone (6b) has a maximum doping density which does not appreciably exceed 1015 cm-3, a width which is comparable with a thickness of the slightly doped zone and a maximum penetration depth which is between 40 μm and 80 μm. The doping density of the guard zone (6b) decreases approximately linearly or stepwise in a direction parallel to the main surface (2).

Pn-junction with guard ring

Es wird ein solches Bauelement mit mindestens drei aufeinanderfolgenden Schichten vorgestellt, das eine hohe Stromfestigkeit und kleine Verlustleistungen aufweist. such a device is presented with at least three successive layers, having a high current capacity and small power losses. Zur Kontaktierung der ersten zwei Schichten (3, 4) besitzt es eine erste(1) und eine zweite metallisierte Kontaktebene (2), die einer ersten Oberflache eine stufenformige Struktur aufpragen. For contacting the first two layers (3, 4) it has a first (1) and a second metallized contact plane (2) which impart a step-like structure of a first surface. Die Stufen sind zwischen 10 und 20 µm hoch und zwischen 20 und 300 µm breit. The steps between 10 and 20 microns high, and between 20 and 300 microns wide. Das Verhaltnis zwischen der Oberflache der ersten Kontaktebene (1) und der Oberflache der zweiten Kontaktebene betragt zwischen 1 und 4. Die erste Schicht (3) ist hochdotiert und maximal 8 µm dick, die zweite Schicht (4) ist niedrigdotiert und maximal 40µcm dick. The ratio between the surface of the first contact plane (1) and the surface of the second contact plane is between 1 and 4. The first layer (3) is highly doped and up to 8 microns thick, the second layer (4) is low-doped and maximum 40μcm thick. Die erfindungsgemasse Oberflachenstruktur wird im wesentlichen durch ein reaktives lonenatzprozess mit einer einzelnen Aluminium-Maske erzeugt. The inventive surface structure is produced by a reactive ion etching process substantially with a single aluminum mask.

Semiconductor power device and method of manufacture

Field controlled thyristors (FCTh) have been realized by a recessed gate technique. Static and dynamic characteristics are measured and compared to theoretical results. During turn-off a new latching mechanism is observed which is explained in terms of a comprehensive physical model. New advanced cascode and cascade circuits are proposed with reduced on resistance, very high current gain and fast, snubberless switching.

Peter Dr. Roggwiller

Papers

Gate turn-off power semiconductor device

Semiconductor devices for power conditioning

Pn-junction with guard ring

Semiconductor power device and method of manufacture

Properties of a high-power field-controlled thyristor