A method and system are disclosed for retrieving information through the use of a multi-stage interaction with a client to identify particular knowledge content associated with a knowledge map. The present invention is an application program running on a server accessed via the world-wide web or other data network using standard Internet protocols, a web browser and web server software. In addition to an automated portion, the present invention allows a human dialog designer to model the way the system elicits information, giving a human feel to the dialog and a better customer experience. In operation, users start a dialog by directing their web browser to a designated web page. This web page asks the user some initial questions that are then passed to a dialog engine. The dialog engine then applies its methods and algorithms to a knowledge map, using dialog control information\ and the user's responses to provide feedback to the user. The feedback may include follow-up questions, relevant documents, and instructions to the user (e.g., instructions to contact a human customer service representative). This dialog engine response is rendered as a web page and returned to the user's web browser. The user can then respond further to the follow-up questions he or she is presented, and the cycle repeats. The invention can be implemented so that it can interact with customers through a wide variety of communication channels including the Internet, wireless devices (e.g., telephone, pager, etc.), handheld devices such as a Personal Data Assistant (PDA), email, and via a telephone where the automated system is delivered using an interactive voice response (IVR) and/or speech-recognition system.

System and method for providing an intelligent multi-step dialog with a user

The present invention provides an architecture and method for a gaming-specific platform that features secure storage (354) and verification (366) of game code and other data, provides the ability to securely exchange data with a computerized wagering gaming system, and does so in a manner that is straightforward and easy to manage. Some embodiments of the invention provide the ability to identify game program code as certified or approved, such as by the Nevada Gaming Regulations Commission or other regulatory agency. The invention provides these and other functions by use of encryption (216), including digital signatures (220) and hash functions (210) as well as other encryption methods.

Encryption in a secure computerized gaming system

A disclosed gaming machine is designed to execute a modular gaming software architecture. A plurality of gaming software modules may be loaded into RAM on the gaming machine and executed to play a game of chance. Many of the gaming software modules are designed to communicate via application program interfaces so that the logic in many of the gaming software modules may be designed independently of each other. In particular, the modular gaming software architecture allows a game flow software module used to generate a game of chance on the gaming machine to be decoupled from a game presentation software module used to present the game chance. Thus, a group of games may be designed where the games share a common game flow software module but use different game presentation software modules to change the look and feel of the game.

Game development architecture that decouples the game logic from the graphics logic

A video game system includes a game cartridge which is pluggably attached to a main console having a main processor, a 3D graphics generating coprocessor, expandable main memory and player controllers. A multifunctional peripheral processing subsystem external to the game microprocessor and coprocessor is described which executes commands for handling player controller input/output to thereby lessen the processing burden on the graphics processing subsystem. The player controller processing subsystem is used for both controlling player controller input/output processing and for performing game authenticating security checks continuously during game play. The peripheral interface includes a micro-processor for controlling various peripheral interface functions, a read/write random access memory, a boot ROM, a coprocessor command channel interface, a player controller channel interface, etc. A peripheral interface macro may be executed to start a read or write transaction with each peripheral device and thereafter transfer the transaction results stored in the random access memory to the game microprocessor main memory.

Video game system using memory module

A disclosed gaming machine is designed to execute a modular gaming software architecture. A plurality of gaming software modules may be loaded into RAM on the gaming machine and executed to play a game of chance. Many of the gaming software modules are designed to communicate via application program interfaces so that the logic in many of the gaming software modules may be designed independently of each other. In particular, the modular gaming software architecture allows presentation state logic to be decoupled from implementations of presentation components, such as graphical, audio and gaming device components, used in a presentation of the game of chance on a gaming machine.

Decoupling of the graphical presentation of a game from the presentation logic

A fully programmable, graphics microprocessor is disclosed which is designed to be embodied in a removable external memory unit for connection with a host information processing system. In an exemplary embodiment, a video game system is described including a host video game system and a pluggable video game cartridge housing the graphics microprocessor. The game cartridge also includes a read-only program memory (ROM) and a random-access memory (RAM). The graphics coprocessor operates in conjunction with a three bus architecture embodied on the game cartridge. The graphics processor using this bus architecture may execute programs from either the program ROM, external RAM or its own internal cache RAM. The fully user programmable graphics coprocessor has an instruction set which is designed to efficiently implement arithmetic operations associated with 3-D graphics and, for example, includes special instructions executed by dedicated hardware for plotting individual pixels in the host video game system's character mapped display which, from the programmer's point of view, creates a “virtual” bit map by permitting the addressing of individual pixels—even though the host system is character based. The graphics coprocessor interacts with the host coprocessor such that the graphics coprocessor's 16 general registers are accessible to the host processor at all times.

External memory system having programmable graphics processor for use in a video game system or the like

A fully programmable, graphics microprocessor is embodied in a removable external memory unit for connection with a host information processing system. In an exemplary embodiment, a video game system is described including a host video game system and a pluggable video game cartridge housing the graphics microprocessor. The game cartridge also includes a read-only program memory (ROM) and a random-access memory (RAM). The graphics coprocessor operates in conjunction with a three bus architecture embodied on the game cartridge. The graphics processor using this bus architecture may execute programs from either the program ROM, external RAM or its own internal cache RAM. The fully user programmable graphics coprocessor has an instruction set which is designed to efficiently implement arithmetic operations associated with 3-D graphics and, for example, includes special instructions executed by dedicated hardware for plotting individual pixels in the host video game system's character mapped display which, from the programmer's point of view, creates a "virtual" bit map by permitting the addressing of individual pixels--even though the host system is character based. The graphics coprocessor interacts with the host coprocessor such that the graphics coprocessor's 16 general registers are accessible to the host processor at all times.

Graphics processor with enhanced memory control circuitry for use in a video game system or the like

An improved method of optimizing the instruction set of a digital processor using code compression. In one embodiment, the method comprises obtaining an assembly language program to be used for the optimization process; calculating the static frequency of each instruction type from the base instruction set; sorting the instruction types by frequency; determining the number and type of instructions necessary for correct program execution; creating a compressed instruction set encoding; re-evaluating the compressed instruction according to the foregoing steps; and generating an instruction set encoding for the compressed instruction set. Improved compressed instruction formats and register structures useful in a processor are also disclosed. A computer program and apparatus for synthesizing logic implementing the aforementioned data cache architecture and pipeline performance enhancements are further disclosed.

Method and apparatus for processor code optimization using code compression

A fully programmable, graphics microprocessor is disclosed which is designed to be embodied in a removable external memory unit for connection with a host information processing system. In an exemplary embodiment, a video game system is described including a host video game system and a pluggable video game cartridge housing the graphics microprocessor. The game cartridge also includes a read-only program memory (ROM) and a random-access memory (RAM). The graphics coprocessor operates in conjunction with a three bus architecture embodied on the game cartridge. The graphics processor using this bus architecture may execute programs from either the program ROM, external RAM or its own internal cache RAM. The fully user programmable graphics coprocessor has an instruction set which is designed to efficiently implement arithmetic operations associated with 3-D graphics and, for example, includes special instructions executed by dedicated hardware for plotting individual pixels in the host video game system's character mapped display which, from the programmer's point of view, creates a "virtual" bit map by permitting the addressing of individual pixels -- even though the host system is character based. The graphics coprocessor interacts with the host coprocessor such that the graphics coprocessor's 16 general registers are accessible to the host processor at all times.

Peter R Warnes

Papers

External memory system having programmable graphics processor for use in a video game system or the like

Graphics processor with enhanced memory control circuitry for use in a video game system or the like

Method and apparatus for processor code optimization using code compression

Programmable graphics processor having pixel to character conversion hardware for use in a video game system or the like.

Programmable graphics processor for use in a video game system or the like