A multicast non-stop forwarding (NSF) router architecture enhances high availability of a multicast router (400) in a computer network. The router architecture further preserves multicast data forwarding through a data plane (470) during NSF recovery of one or more failures in a control plane (410) of the router(400). Various multicast components of the router (400) cooperate to provide a checkpointing and recovery technique of the multicast NSF architecture that enables efficient restart and recovery of the control plane failures without loss of data connectivity. In addition, a technique prevents multiple multicast forwarders from forwarding multicast packets for a route over a link in a computer network during NSF recovery of one or more failures in a control plane (410) of a multicast router (400).

System and method for preserving multicast data forwarding during control failures in a router

A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

Self-healing chip-to-chip interface

An artificial synapse array and virtual neural space are disclosed. More specifically, a cognitive sensor system and method are disclosed comprising a massively parallel convolution processor capable of, for instance, situationally dependent identification of salient features in a scene of interest by emulating the cortical hierarchy found in the human retina and visual cortex.

Apparatus comprising artificial neuronal assembly

A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells for permitting exchange of data packets between said array of cells and components external to said array of cells. Each cell communicates with at least one other cell of the array, thereby permitting an exchange of data packets to take place between the cells of the array. Each cell includes a memory for receiving a data packet from another cell of the array as well as a control entity to control release of a data packet toward a selected destination cell of the array at least in part on a basis of a degree of occupancy of the memory in the destination cell. In this way, scheduling is distributed amongst the cells of the switch fabric.

Cell-based switch fabric with distributed scheduling

A ring interface is coupled to a current node in a ring network having a plurality of nodes and corresponding ring interface for each of said nodes. The ring interface includes a ring input port operative to conduct upstream message packets from a previous node to the ring interface, a ring output port operative to conduct message packets to a next node of the ring network, and a bypass queue operative to buffer message packets. A receive queue buffers message packets before passing them on to the current node. An address filter is coupled to the ring input port to receive the upstream message packets, read their destination addresses and pass them to the bypass queue if the addresses correspond to another node and pass them to the receive queue if their addresses are that of the current node. A transmit queue buffers message packets from the current node and a bypass-transmit queue arbiter is coupled to outputs of the bypass queue and the transmit queue and is operative to select message packets from one of the bypass queue and the transmit queue in accordance with predetermined selection criterion and transmits the selected message packets to the ring output port.

Ring interface and ring network bus flow control system

A fault tolerant multicast ATM switch fabric is constructed as a multistage interconnection network through which cells move from input to output along a pre-established data path. The control phase proceeds concurrently with the data phase by which cells move continuously without idle clock cycles in between. The control logic resolves the state of the switching elements and sends this state information to the data path logic ahead of the cell transfer. The switch consists of three IC designs: control, data path, and switch port controller ICs. The successful realization of the switch relies critically on the design of the control IC which incorporates a new combinatorial hardware design running a dedicated algorithm. A switch port controller delegates, based on local decisions, the replication and routing of multicast cells to a selected group of switch port controllers on a per call basis, thereby supporting any multicast group in a unified manner. The ATM cell switch fabric includes a protection control IC for providing a 1+1 protection and a protection data path IC for providing a 1:m protection. A large scale cell switch fabric is constructed in which a first stage switch distributes its incoming traffic, destined for the same output switch and on a per call basis, evenly over multiple routing switches in a 2-stage or higher configuration. A higher switching speed is achieved in which a source switch port controller distributes its incoming traffic, on a per call basis, evenly over multiple cell switches.

Peter S. Y. Lau

Papers

Fault tolerant multicast ATM switch fabric, scalable speed and port expansion configurations